In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion.
I look at the .syr output file from XST, and it claims to have read the file. But...
If I hook a logic analyzer up to the output of the memory, it looks like it never got initialized.
Another problem I'm seeing is that XST appears to not like having an address line (@000) in the file. Also, if the the file is too short, XST complains and discards the initialization.
I'll dig into this some more, but I was wondering if anyone had had any success with this.
Thanks!
John Providenza