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Re: Ask the hotline, you may be surprised and pleased
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 Interesting.
 So this is stress-time effect, that causes a degrade in leakage spec ?

 What time/uA orders are we talking about here ?

 Does this never cause a more drastic point failure ?

 Any idea why Lattice quote a MAX of 64 pins at IO MAX voltage stress
levels ?  (I'm bemused at how the 65th pin knows the state of the other
64 :)

- jg

Re: Ask the hotline, you may be surprised and pleased
Jim,

I will try to add to our knowledge below,

Austin

Jim Granville wrote:

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Yes.  It is interesting because it does not follow the "accepted" failure
mechanisms, and is being studied by many (not at all new, just new to us because
it is the first time we have used this particular .25u pmos transistor for 3.3v
IO).

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In one set of early tests before they improved the process, we saw 6uA in 10
weeks with a peak voltage stress of ~4.5v.  The leakage started out in the nA
range.  Traditional gate breakdown is defined as a 100x increase in leakage, but
it is then usually followed by a complete gate breakdown.  The leakage stopped
increasing.

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Not in the testing we did.  That is what we found strange, and led to a reading
of some of the more obscure papers on voltage stresses in the public literature.

"Defect generation and breakdown of ultra-thin silicon dioxide induced by
substrate hot-hole injection" by Eric M Vogel, Journal of Appplied Physics, V90,
N5, 1 September, 2001....as one example of bedtime reading.  We concluded that
the mechanism described by this paper was NOT what we saw, but then, it wasn't
any of the other ones folks know about, either.

Baking the device at a high temperature also did not make the device recover (as
would be expected from hot electron damage, for example).

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There is no agreement on how to spec this:  the area under stress (number of IOs)
and temperature figure prominently in the models, but had virtually no effect in
the tests we conducted.  Now, of course, we have to stress it enough to see an
effect  (in our limited lifetimes), and one can say with some confidence that
such a stress is not going to lead to the actual failure mechanism, but may be
causing a new, and artifical failure mechanism.  Thus, we combine the older
techniques and models, with the latest data and guesses, and error on the side of
extreme caution so that we can state that if you do not exceed the abs max
numbers, the part lives it regular life.

So, 64 IOs may be just under the 15 or 20 year life projection model limit, and
65 IOs may be just over the limit in the model.  Our experience was that the
number of IOs under stress did not make a measurable difference.  I agree that it
is pretty hard to imagine that having a next door neighbor with a hot plate
increases your chances of burning down your house, but it does make sense that
overall, the more devices you have under stress, the sooner one would expect a
failure........even if we did not see that in our testing.

The most recent tests did allow us to relax the bank requirements for V2P, so now
all banks may operate at 3.3V, and it will not affect the lifetime nor the
reliability of the part (as opposed to the original banking restrictions).

It could be that they have not seen the same results in their testing from their
fab?  Turns out this is very tricky stuff, and implants, layout, etc affects the
performance of these devices under these extrememly high field stress
conditions.  There is a magic recipe that one finds, and then sticks with it
(just like any other IC process).




Re: Ask the hotline, you may be surprised and pleased
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it
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Yes, I'm sure it's some arbitrary FIT number, or could be some test
equipment
limit :) - but it does raise the eyebrows ....

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now
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their
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the
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Thanks, interesting summary.

 I recall seeing a note from Philips research a couple of years ago,
about
a breakthrough in high voltage devices (> 100V) in (IIRC) 0,5u process.
 Seems what they found was thinner worked better, the opposite of what
E field stress would suggest, and they concluded it was because the
'loose electrons' has less time to accelerate, and so had less energy
with which to do serious damage :)
 Does show there is no substitute for bench tests...

-jg

Re: Ask the hotline, you may be surprised and pleased
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back to the driver do to the driver,
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one of the 200+ hotline CAEs to get
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you get multiple answers...) It
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their mistakes, and improve their
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closing the loop!
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doesn't work, let us (me) know.  You
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appreciate the slamming of our hotline
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I don't understand why you feel the need to shoot the messenger.  The
hotline staff of most companies is just as Lecroy described, eager to
end the call as that is how they are evaluated.  Xilinx is no exception
and this has been noted here on more than one occasion.  

This newsgroup is a place of all of us to share our experiences and
opinions and I, for one, don't appreciate your criticism of Lecroy's
post.  If you feel his experience is not typical, then feel free to say
so, but certainly you have no expectation that he should not express his
experience or opinion.  


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parts, not "closed
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amount of time, it is escalated.  Once
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the issue.

That is your opinion of how the process works.  Many people have had
different experiences.  Often it is not escalated until the customer
requests.  Overall the experience can be so frustrating that the
customer doesn't push very hard to get a real answer and gives up after
a few conversations.  

Anyone can be in denial about a problem with their company.  But that
does not make the problem go away.  The problem is also not eliminated
by comparing yourself to your competition and saying "we are better than
they are".  It can still be a problem.  


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Rick "rickman" Collins

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Re: Ask the hotline, you may be surprised and pleased
Rick,

Here is my 5th try to respond.  Maybe I will send it.

See below.

Austin

rickman wrote:
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doesn't > work, let us (me) know.  You
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appreciate the slamming of our hotline
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I did not shoot him.  I merely mentioned that he should try to get support
through the normal channels.  And if that
did not work, to contact the folks who are watching the watchers.  And not slam
a service that he did not use.

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Perhaps in your mind, but to us it is deadly serious, and we deny that your
comments are accurate, or truthful.  Sure,
one can get a bad answer, or a wrong answer, and occasionally an answer that did
not meet your timeline;  but if that
case is closed before you say you are happy, it is cause for dismissal.

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OK.  Like you said, all opinions are welcome.

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I did.


He is free to say anything he wants, as are you.

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sells    > parts, not "closed cases."  If
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of time, it is escalated.  Once
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resolve the issue.

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No, that is the way it does work.  I helped re-write it.  And audit it.

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Then let Peter and I know:  I want dates, case numbers and names.  I want to
know of any unhappy customers anywhere.
And yes, I would prefer it sent directly, not the newsgroup, so we can research
it properly, and get it resolved ASAP.

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Uh, that is how it works, the proceedure is that the customer has to say how
urgent the matter is AND the time limits
have to start getting exceeded.

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Haven't met any like that.  Perhaps there are those who are so timid they can't
use a hotline?  The customers that I
meet are not shy at all about demanding the best service.  And right now, if
they don't get the answer, they are likely
to be part of the next layoff, so it is hard for me to see how a customer would
not make every effort to get their
problem resolved.



Re: Ask the hotline, you may be surprised and pleased (but not likely)
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doesn't > work, let us (me) know.  You
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appreciate the slamming of our hotline
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through the normal channels.  And if that
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slam a service that he did not use.

You didn't shoot him with a gun, but you criticized him for "slamming"
your service which he *HAS* used and found to be lacking.  


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comments are accurate, or truthful.  Sure,
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did not meet your timeline;  but if that
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I also like the way that I get survey requests on every case, but I have
never heard back from anyone when I fill one out and indicate that a
case was prematurely closed or the result was otherwise unsatisfactory.  


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And receive criticism for giving his experiences.  


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sells    > parts, not "closed cases."  If
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of time, it is escalated.  Once
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resolve the issue.
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But you don't execute it.  As far as I am aware you have not monitored
any of the cases described here either.  I don't believe you are in the
chain of command for the hotline.  The bottom line is that you feel the
hotline works one way and many of us have different experiences.
Obviously our experiences are only "in our minds".  


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know of any unhappy customers anywhere.
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research it properly, and get it resolved ASAP.

It is seldom worth an engineers effort to persue a hotline case for more
than a couple of days, much less follow up with a bad case.  If you want
to follow up on poorly handled cases, why aren't the surveys read and
responded to?  


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urgent the matter is AND the time limits
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So if a customer does not know that there are levels of support and the
person providing the support has run out of ideas, the customer is
expected to figure out to ask for a higher level?   Sounds pretty silly
to me.  Once engineers get familiar with support that may be automatic,
but I remember my experiences with support and just how long it took me
to learn how to navigate the support pathways to try to get to someone
who actually knows about the problem.  

I have also had the first level of support refuse to let me talk to the
engineer who actually knew something about the problem.  Instead he
insisted that he be my point of contact and that he would relay the
information back and forth to the other engineers.  Unfortunately this
required several relays just to get the question across since the second
level support kept believing that the first level was relaying the
question wrong.  

The bottom line is that many engineers refuse to contact support even
when told to.  Their experience has led them to feel that the whole
process is poor and not worth the effort.  

You can believe what you want, but this is what I have found at most of
the companines where I have worked.  This is not just my opinion, but
that of many engineers.  


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can't use a hotline?  The customers that I
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they don't get the answer, they are likely
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would not make every effort to get their
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<sarcastic mode on>
Yes, I think you are right.  The problem is not with the hotline, it is
with the customers.  Of course the hotline has been designed to provide
the best level of support under all conditions and any customer who has
less than a fully satifactory experience must have been poorly trained
or is suffering from a personality disorder.
<sarcastic mode off>

Denial is not just a river in Egypt.  

Enjoy your boat tour Austin.

--

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Re: Xilinx S3 I/O robustness question
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excursions are, an be sure they stay
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That is a *very* important question.  We have seen the timing files go
through iteration after iteration of refinement.  At what point can be
believe that the IBIS models will be stable?  


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get the "final word" from the
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Rick "rickman" Collins

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Re: Xilinx S3 I/O robustness question
It appears that Xilinx does not care to discuss their models.

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excursions are, an be sure they stay
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will get the "final word" from the
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Re: Xilinx S3 I/O robustness question
Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models.  Are you looking
into it?  Is the part just to new and there is no information
available at your level?

Re: Xilinx S3 I/O robustness question
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No one has responded to my posting here.  This is not the sort of
question you can expect a good answer from by the hotline.  So unless my
local rep can give me some straight talk, I will assume that the IBIS
models are still very preliminary and not of any real value for
simulation yet.  BTW, I am having breakfast with my rep and sales person
today.  We'll see what they have to say about the IBIS models and the
partial reconfiguration issues.  

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Re: Xilinx S3 I/O robustness question
Rick,

The IBIS models are based on the foundry spice models, which are pretty
mature now, as the same transistors used for the IOs have been manufactured
now for almost a year.

Just because others have absolutely lousy IBIS models out there does not
mean we do:  We continually check the quality of the models.  Yes, Spartan 3
has preliminary models but only because it is not released to production yet
-- it is still int he ES phase.  This allows us to make changes easily as we
discover issues.  So far, no issues with IBIS.

Austin

rickman wrote:

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Re: Xilinx S3 I/O robustness question
Thanks for the answer.  

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Rick "rickman" Collins

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Re: Xilinx S3 I/O robustness question
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From a Xilinx S2 IBIS model..  
Note " .... this model is considered preliminary as it has not been
verified by actual silicon measurement."
And this is an old part.  How good do you think Xilinx models are for
the S3??


[Disclaimer]     The data in this model is derived from SPICE
simulations using
                 modeling information extracted from the target
process. While
                 a great deal of care has been taken to provide
information
                 that is accurate, this model is considered
preliminary as it
                 has not been verified by actual silicon measurement.
Treat the
                 data in this model as preliminary until actual
silicon
                 verification is performed.
[Copyright]      Copyright 2000, Xilinx Inc., All rights reserved

Re: Xilinx S3 I/O robustness question
Standard disclaimer.

We don't seem to get around to removing the caveats.....I'll look into that.

All parts once they are in production have been verified in MY lab.

By the way, folks have asked about duty cycle distortion in the outputs, and IBIS
models will allow you to simulate the FAST/STRONG corner and then the SLOW/WEAK
corner.  You can imagine that the rise vs. fall times could be (absolute worst
case) that different.  Godd thing to check when you want to know "is this
standard
fast enough for my xxxx application?"*

Austin

This does use the low vcc, low temp, high vcc, high temp as part of the corners
(as well as the process variation which is what you are really concerned about
here), so it is more pessimistic than the reality (reality can not have a low
vcc,
hot rising edge with a high vcc cold falling edge), but it is still a great way
to
check if the IO standard you have chosen is reasonably well matched for the speed
you desire.

lecroy wrote:

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Re: Xilinx S3 I/O robustness question
Hi Peter,
      If the pin has 10 Ohms of drive impedance the initial sent pulse
will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10
Ohms driver drives a 50 Ohm line. The reflected signal from the
unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse
then increases the voltage at the pin to 3.667, as it's driven from 50
Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the
absolute maximum rating of 3.75V. Hooray!
      As you say, this calculation disregards the attenuation due to
the trace propagation function, which will further reduce the
amplitude of the pulse as it travels back and forth down the
transmission line(pcb trace). This is caused by skin effect and stuff.
I guess you could also reduce the drive strength of the pin from the
default 12mA, to increase the source impedance.
       The receiver pin is the one that gets the big hit.
        cheers, Symon.


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Re: Xilinx S3 I/O robustness question
Symon,

As if often the case, if you do not run a simulation, you will not get results
that are
even close to the truth (by guessing at what is happening).

With a driver impedance of 8.8 ohms (from IBIS simulation), the
overshoot/undershoot back
at the driver is less than 100 mV (no pcb or t-line losses, IBIS done with
Hyperlynx).

Why does this not scale exactly as you state?  Because the ON resistance of the
transistors is not very linear, and they are less than 8.8 ohms near Vcc or
ground.

So, unless you simulate the actual circuit, you will not get the actual result.

Austin

Symon wrote:

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Re: Xilinx S3 I/O robustness question
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So how bad is that hit?  How good are the protection diodes?

If the clamp diodes are any good they will reduce the reflection
and make things easier back at the transmitter.

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Re: Xilinx S3 I/O robustness question
Hal,

Simulation includes a receiver at the end of a 2ns line, and you are correct, it
makes things better.

Why simulate a driver drving nothing?  Unless of course that is a possibility in
a system....not a very useful system, though....

Austin

Hal Murray wrote:

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Re: Xilinx S3 I/O robustness question
Austin,

Did both a 440 ps and a 2ns line.  Not to confuse.

Austin

Austin Lesea wrote:

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it
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in
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Re: Xilinx S3 I/O robustness question
But if you are simulating to check the possibility of damage, it seems
reasonable to allow for an unconnected trace due to a component being
left off a board intentionally or not or the possiblity of an open trace
on the board.  I don't think many people would expect an open trace to
be the cause of a chip failure in a properly designed board.  If you
don't analyze for this, a chip may have a higher than expected failure
rate due to typical repairable board defects.  


Austin Lesea wrote:
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it
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in
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Rick "rickman" Collins

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