Xilinx S3 I/O robustness question

But if you are simulating to check the possibility of damage, it seems reasonable to allow for an unconnected trace due to a component being left off a board intentionally or not or the possiblity of an open trace on the board. I don't think many people would expect an open trace to be the cause of a chip failure in a properly designed board. If you don't analyze for this, a chip may have a higher than expected failure rate due to typical repairable board defects.

Aust>

it

in

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This is a good question. So far I have only read people considering the S3 chip driving. What about the case where is is on the receiving end of the signal?

My designs typically don't consider signal integrity on traces other than edge sensitive clock lines and chip enables. For non-edge sensitive signals, I have always treated it a bit like metastability, allow some time for the signal to settle out and all will be good by the time of the clock edge. But if we have to consider *every* trace on the board for reflections and overshoot, board design can become a nightmare!

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Rick,

Good point, and without the termination (load or receiver) the difference is:

100 mV higher (lower) peak voltage (+/- 237 mV from Vcco and ground).

Still well within the datasheet limits.

Again, simulate what you are doing!

Aust> But if you are simulating to check the possibility of damage, it seems

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addresses.

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Rick,

You are going to have to consider the receiving end SI.

In addition to violating the specifications (possible) you can also create EMI/RFI, and cause substatial substrate and Vcco bounce by slamming the clamp diodes at the inputs. The bounce leads to changing the substrate (ground) and Vcco on die, which causes jitter, and timing failures. All of this is trivially prevented by choosing the right series termination at the driver (or using DCI drivers).

With the Vccint at 1.5V and dropping fast, ground bounce is now becoming public enemy number 1.

Like I said, you can't get around LA without a car. Get the simulator. Use it.

Aust> Hal Murray wrote:

Hi Rick, As a rule of thumb, when the signal's rise time is faster than

1/6th the time for the signal to get to the other end of the trace, (guess at 170ps/in of track) then you MUST consider the SI implications. (So for a 1ns rise time, i.e. a normal 'FAST' Xilinx pin, you can have 1 inch of track before you have to worry about reflections!) You can find the rise time data in the IBIS files Xilinx provides on their website. Remember, the frequency of the signal isn't important, it's the rise time. Leave those pins in 'SLOW' mode whenever possible! As Austin says, the simulation tools are a BIG help here. Those IC pins drive bloody hard and fast and I would never like to be relying on the clamp diodes to save the day, this dumps energy into the supplies and Austin is not joking when he says that ground bounce is (and will continue to be) a big consideration. There's a reason Xilinx have gone to the trouble of putting DCI on their devices! The receivers warrant the most attention as they can appear as an open circuit, the drivers have low impedance and so limit deviations a bit better. It's time to dust off "High-Speed Digital Design" for some bed time reading! There's a new edition out I believe? (Just found it:- High-Speed Signal Propagation: Advanced Black Magic) I also recommend also by Dr. Howard Johnson. More v. helpful stuff there for free!! HTH, cheers, Syms.

But your use of the term "must" is not totally accurate. The numbers you give are a good rule of thumb for when reflections will be significant to the signal waveform, but that does not automatically indicate a problem will be created. A data line can bounce around for an extra ns or two and won't matter if there is extra time in the setup. Up until now I have not seen a chip rated to exclude ringing or overshoot (or undershoot) because of damage. In fact, most data sheets specifically say that this will not be a problem if it only persists for a few ns.

I have not heard of ringing being the cause of ground bounce. My experience has been that ground bounce is caused by the initial current slug when an output changes state, not the result of a reflection from the other end. As the numbers that have been posted in this thread have indicated, the reflection current is much smaller than the initial slug.

If I actually have to simulate every signal on the board I am designing, it may never get done. I think there is something wrong with the idea that this is a overly complex issue and can't be dealt with in a simpler manner. Or am I missing something of what you are saying?

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Rick,

Fight it as long as you can, but everyone else is using the more advanced tools, and simulating everything (at the companies where they want to be successful on the first pcb turn -- as for the others, I don't hear from them often anymore....).

And yes, if you do not pay attention now, you will cause ground bounce (50 -

60 mA of reflection current per IO is possible), and with the Virtex II Pro, and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max data sheet limits if you do not pay attention to what you are doing. And that will cause a reduction in the 20 year projected lifetime. Below 3.0V, there are no reliability issues to consider, as the clamp diodes are sufficient to protect the IOs. Smaller, faster, less expensive technology from the foundries has some drawbacks: leakage current, and IO robustness at voltages greater than 3.75 volts being two of them.

The new tools allow for extraction of all pcb parameters, and easy simulation of all tracks/traces. You can also create a design that is correct by construction: use DCI or series or parallel termination, and make 50 ohm (or whatever) traces. Then you do not have to simulate everything.

Or use a standard: HSTL, SSTL, PCI. Then you also don't have to think. But I also simulate to make sure I haven't missed anything.

Aust> Sym> >

[snip]

(50 -

[snip]

Austin,

I appreciate your continued push to get us to look at signal integrity more closely but please help me out here. "Ground bounce" that I'm aware of involves shifting voltage reference thresholds - a voltage effect - due to the parasitic inductance of the chip's ground to the board's ground plane. The change in current draw (dI/dt) across the package inductance produces the voltage change.

Are you suggesting the voltage effect will be caused by the current change due to reflected energy getting absorbed in the transistors driving those signals to ground? This would make some sense to me though I would expect the current surge to be spread over a much larger time (different open-circuit lengths) than the original current surges that generated the synchronous signals getting the reflection.

If my interpretation is not correct and you're suggesting ground-bounce is related to current rather than current-change related voltage, please help me understand.

If logic-high reflections are suspected of causing ground bounce, I'd appreciate some elaboration. Is there a path for this current through the ground on-chip? Are the voltage references not entirely ground-referenced?

Thanks for your help.

John_H,

Take a simple CMOS inverter inside the IC (not part of the IO). Its switching threshold is directly related to its ground reference, and its Vcc reference. Any ground bounce (LdI/dt) or Vcc bounce (same formula) will move ground and vcc around, even in a perfect bypass world, as there is no "C" used in the spelling of "LdI/dt."

Basically, assuming perfect bypass caps, a perfect AC short, you still have that damned LdI/dt to deal with, and the only way to deal with it is to reduce L, dI, or increase dt, or don't switch everything at once (switch banks on different phases of the clock).

Now add to the dI/dt that comes from switching outputs, you have a transmission line with signals launched from chip 1, towards chips 2, and at chip 2, the overshoot and undershoot of the mismatched signal to the t-line causes the input clamp diodes to become forward biased. Now you have a current, and it is changing, so now there is an additional dI/dt into Vcc, or out of ground at the RECEIVER. From the clamp diodes, this current has to traverse the same path as an output switching current, that is through the various metal layers, and the package, to get to the ground and Vcc planes in the pcb, so LdI/dt appplies for these signals (inputs at chip 2) as well, and because of the mismatch, overshoot and undershoot, you add to the ground bounce/vcc bounce that is from chip 2's outputs.

All of this shifts the switching threshold of that poor inverter (in chip 1 or

2), and the result is much more jitter than you suspected was in the design.

I have not even taken into account what dI/dt results from the reflected wave as it comes back to the alread ON driver transistor in chip 1 (the TRANSMITTER), and then has to go to/from Vcco and ground, which is another added LdI/dt on top of the previous LdI/dt from the intitial switching of the output transistor (just will make things worse from not being matched).....

To look at currents in a simulation, place a 1 ohm resistor in series with the line, and then you can see just what dI/dt's are happening.....(so every

1mV=1mA)

Aust>

Is there a good market there? If a 5 inch 32 bit data bus without termination precludes passing CE/FCC RFI tests, then no PC would ever be sold. Few RFI issues are solved purely at the PC board level. In US commercial markets, the requirements are very different than consumer markets as well.

That is assuming that the diodes would be triggered. I seem to recall that the basic analysis done here showed that this was unlikely.

That is the part I am not clear about. These traces are all individual circuits. If you have the luxury of a lot of open board space to route straight lines here and there, then sure, you can make each one very similar. On a small, tight board it will be very difficult to make them that similar. If the signal is critical enough to require a simulation, then I expect I would need to simulate each of them.

I am surprized that the Spartan 3 chips are so sensitive to over and undershoot that this has become a major issue. I have seen lots of high speed boards and none had FPGAs or any other chips that needed this degree of analysis to prevent damage.

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Funny. But I doubt it is very accurate. I have worked at some of the larger companies making telecom test equipment and I have yet to meet a board designer who simulates all of the traces. The ones I spoke with only simulate the clock lines or other signal lines when the timing is tight with no time for settling.

Like I said, this is the first time I have heard a chip maker claim that typical ringing and undershoot can cause chip damage. Of course an absurdly designed trace and create excessive swings. But the typical amount of ringing is normally listed in data sheets as being within spec for chips.

Under what conditions is this "possible"? I would expect this to be an extreme case. The analyis listed here indicated much lower currents (~35 mA) and only for the brief time (< 1 ns) of the overshoot. If the device can't handle these low currents without ground bounce, how can it possibly provide the much larger currents (> 55 mA) for the initial level change without ground bounce?

So the DCI in the S3 chips will allow matching of the chip IO impedance to the trace, right?

I only wish standards really did preclude the "thinking". I have worked with RS-232 and many others too long to beleive that.

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Rick,

Get off that horse: 'typical' ringing is not the issue here.

Have said it a number of times: overshoot and undershoot is bad (period), and is a sign of a bad board design. The fact that if you have

1) 85C Tj AND 2) you have a power supply at 3.6 volts AND 3) you have crappy SI over long t-lines (which store more energy -- like 12 - 24")

MAY lead to exceeding the Abs Max spec.

The point is that you have to simulate to get good SI, so do so. While you are at it, if the SI is terrible, fix it. If you can't fix it, then make sure you are within the Abs Max specs.

Aust> Aust> >

Last post:

See below,

Aust> Sym> >

Yes, you can sell garbage. I don't think that we are talking about that here: even game toys have to have just about every government and safety lab certification known....

They are triggered at the receive end. Remember the low drive impedance, high terminate impedance t-line case tries to as much as double the voltage at the receive end. Remember Howard running across the room with his pointer and banging into the wall (if you have been to one of his great performances)? Instructive.

Yes.

Get off the horse. It is tired already. See my other post. If you are going to have really bad SI, at 3.6V Vcco, AND 85C Tj, then you may have to consider the abs max specs.....so do a good SI job, and you will never get there.

In previous families, there were Abs Max specs, and you could go past them, too, with poor SI. This is only different because the numbers are tighter, and the Vccint is now 1.2 volts, and bad SI will make the design fail to function a long time before any IO will fail. Why not encourage designers to be successful (hey, what a concept! if the design works, then we sell more chips!).

I find your tone offensive Austin. I am simply trying to understand the issue being discussed by yourself as well as others. On my board there will be no traces that are near 12" much less 24" and the power supply will not be 3.6 volts. So what you are now talking about is not a typical board design, but rather a *bad* board design. That is not what you said. Your statements, as well as others, was that *every* board needs to be simulated. I agree that clock signals are very sensitive to signal integrity, but most data lines, that are not excessively long, will do no hard to most chips and SI issues will only add to the setup time.

So if my traces are 6" and under and my Vccio is 3.3 volts or less, is it likely that a data trace will be at issue if it is not simulated? As I said, this is the first time I have heard anyone say that it can be an issue, *especially* an issue of doing damage to a chip.

Ringing has been an accepted part of digital logic design since logic was invented. It is a problem, not because it exists, but only if it creats a malfunction. It can ring for an hour and I won't care if I have two hours of settling time on my bus.

If you don't wish to discuss this politely, then please feel free to ignore my post.

Aust>

is

24")

are at

-

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Thank you for that comment Austin. You are the first person to ever call my work garbage.

That is the part that is not practical and I don't believe that it is required for most signals. Of course, the sensitivity of the Spartan 3 chips seem to place new boundries on ringing and SI. According to what you are saying, signal ringing can do damage to these chips while most chips in the past have not been that sensitive to it.

As I said in my other posts, I have been reading absolute max specs for years and many have specific exclusions for the brief time of over (or under) voltage due to ringing. A couple of ns of overvoltage has never fried a chip in any lab that I have worked in.

I understand. But your comments seem to be self contraditory. First you tell me the issue is SI which is common to all boards and then you say the issue is the extreme sensitivity of the new Spartan 3 chips to SI. SI is always relative. In the past the threshold of failure had to do with delayed settling or double clocking of edge signals. Now these new chips are much more sensitive to a new issue, SI induced failure. That is all we had to say and admit.

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Cutting thru the words... I will have to agree with Austin here.. as speeds go up and voltages go down simulation is going to go from "well maybe" to "essential"...

Sure your 12 MHz 8031 micro will never need to be simulated.. but your 800 MHz LVDS bus may not even work.. is just a matter of getting relative and you will find the same with your FPGA... fast edges and fast clocks will stir a hornets nest .. just be prepared for them..

and you think this is bad .. wait for the Spartan 4 at .6 instead of .9 .. give it a bad look and it will jump of the board .. but it will probably run at a Gig and run on an oily rag

Simon

[snip]

Rick,

Sorry to have offended, but you really are arguing a lost cause. Ignore SI? At your peril. And not (just) for relibility reasons, just plain work reasons.

As for your example, of less than 12", and 3.300V, again, I ask you to go simulate the exact situation you are asking about.

What impedance trace? What strength driver? What is(are) the load(s)? What is potentially coupling to the trace(s)? Too many variables to just say: "hey, no problem."

By the way, I would never state "hey, no problem," as Murphy says, "whatever can go wrong, will go wrong...." that is why we simulate.

Aust> I find your tone offensive Austin. I am simply trying to understand the

and is

- 24")

are at

are

(50 -

3.0V,

technology

robustness

PC's only pass because they're in metal boxes. Not everyone has that luxury!

What I do is arrange the signal pins on my FPGA so they connect 'one to one' to other devices. Worry about pin swapping signals inside the FPGA fabric. Together with careful board layout, you can keep the buses a nice regular structure. This keeps large numbers of tracks similar. The PCB layout people like me too!! To me this is a BIG advantage that FPGAs offer.

I don't think the Spartan-3 is especially oversensitive per se, just that low voltage, small geometry parts are likely victims. It's something to consider in more and more designs as time goes by. The FPGA is often the device that connects a lot of disparate pieces with varying signalling standards together so deserves special attention.

Anyway, I've enjoyed (am enjoying) our discussion, I'm sure any (hopefully) small offence caused by some posters' robust I/O and others' sensitive inputs can be put down to a mismatch in transmission standards!! Maybe we should terminate this before the noise going back and forth gets above the absolute maximum tolerance! All the best mate, Syms.