fitting Xilinx CPLD - I/O Pin Termination

It is not the same as Programmable GND Pins on Unused I/O. I can choose between Keeper and Float. There is no information about this property.

Reply to
Valentin Tihomirov
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Look at the 'bus bold circuitry' in the XC9500XL date sheet and at answer #5175 in the Xilinx answer data base.

Best regards

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Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it
Reply to
Klaus Falser

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