It is not the same as Programmable GND Pins on Unused I/O. I can choose between Keeper and Float. There is no information about this property.
fitting Xilinx CPLD - I/O Pin Termination
Nov 11, 2003
1 Replies
Look at the 'bus bold circuitry' in the XC9500XL date sheet and at answer #5175 in the Xilinx answer data base.
Best regards
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it
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