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Xilinx MIG DDR2 Documentation

I am trying to use the Xilinx Memory Interface Generator (MIG) version

1.6 to generate a DDR2 x16 core for initiall testing of a XC4VFX12-10SF363 board that we are bringing up this week. The memory is a Micron MT47H32M16BT-3. After some challenges, not the least of which, MIG doesn't want to run from CORE Generator; the standalone user interface needs to be guessed, as all data isn't passed through the GUI... I have generated a core in VHDL that seems to be quite similar (but not exactly) to XAPP721.

I hope this isn't an RTFM question... as I can't find the manuals to read...

Has anybody:

A) Used MIG to generate a DDR2 core in x16 configuration for V4? (Antti, from one of your previous posts, I think you have a yes answer to this)

B) Found any meaningful documentation of the MIG and/or the DDR2 core specifically? (The user guide that comes with it is a little light.)

C) If yes to A, what docs did you find the interface spec in? or did you just start reading the source code?

I am using ISE/EDK 8.1 and MIG 1.6. I will probably have to move this project to 8.2 by the end of the week for various reasons. For the short term this seems like a decent moderate-performance way to get a x16 DDR2 onto a x64 PLB bus. Long term we will need to write our own core to get the performance we need, but for the next few weeks, this will be fast enough.

D) Am I overlooking any obvious quick and dirty paths to getting a x16 DDR2 onto a x64 PLB? (I did not see anything in EDK.)

E) Am I in for a world of hurt going down the path that I have selected? (Positive experiences with MIG would be reassuring.)

Thanks for the help in advance. I will start a case tomorrow with X... in the meantime I would appreciate it very much if somebody had some experience that he wants to share.

Regards, Erik.

--
Erik Widding
President
Birger Engineering, Inc.


 (mail) 38 Chauncy St #1101; Boston, MA 02111
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Reply to
Erik Widding
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I found the documentation that I needed... turns out it was an RTFM question for the most part.

Though, if anybody has any direct experience with MIG 1.6, DDR2 x16 used in V4, I would love to hear how it went.

Regards, Erik.

Reply to
Erik Widding

We have an SX55 design with DDR2 mini-DIMM (72-bit data path). I used MIG 1.5 instead of rolling my own controller. I only had a few problems; I had to play with the clock phases of commands and data to get the read data to come back at the right time. One thing I would recommend is to change out the FIFO16 in the command path. It had a tendency to go empty but not update the empty flag, so it would execute the same command over and over again. Replacing the FIFO with one created by CoreGen was an easy fix.

The downside to the MIG is that they only allow one bank to be open at a time. Peter hinted that the V5 MIG designs will allow multiple banks to be open. I'm hoping that this migrates to teh other designs.

--
Joe Samson
Pixel Velocity
Reply to
Joseph Samson

Hi,

I have used MIG1.6 from coregenerator to generate DDR2 Controller Blocks (1st- 64-bit (4 x16-bit), 2nd - 32-bit (2 x16-bit).

You can find the documentation in docs directory of generated files.

MIG documentation is good start along with XAPP702 and 703 app note.

Had some problems with calibration - which the xilinx controller does to get delay values for IDELAYCTRL blocks. Still working on with it.

Regards Rao

Reply to
rao

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