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Xilinx MAP problem (>1 External Macro Output Pin on single net)

Hi Everyone,

I would be really for any help or advice you can offer me on the following.

I have created a simple tri-state bus as a macro using xdl. The design consists of two TBUFs driving a single long line.

(Diagram at

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I attach external macro pins to Out, Enable and In of each TBUF. However, when I try to include the macro in a design, the DRC in the map phase complains that the Out pin is being driven by two sources. MAP Error Message:

ERROR:MapLib:22 - Bus M0_DATA_LEFT_O_OBUF driven by bm_instance and bm_instance has multiple active drivers.

This is not correct, as the O pins are external macro outputs! Is there anyway to prevent this?

Xilinx don't list any help for this Error.

/Ian.

Reply to
Ian
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What device are you targetting? Newer FPGA's don't have TBUF's anymore. CPLD's never did...

Reply to
Gabor

I am targeting Spartan 2 devices.

Reply to
Ian

There's a fitter option somewhere that tells the tools to converter internal tristates to muxes. Find that option and tell it not to do so.

-a

Reply to
Andy Peters

Will that have any effect on a pre placed macro?

Andy Peters wrote:

Reply to
Ian

It may be that you have confused map by defining both TBUF outputs to be external macro pins. Since both TBUF outputs are connected to the same net (internally in the macro) you only need to define one of those outputs to be an external pin.

-Pete

Reply to
Pete Sedcole

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