Xilinx LogicCore Direct Instantiation

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Toolset: ISE/ModelSim_PE/VHDL

I've been asked to modify one of my designs for another application
so decided it was time to parameterize it as much of it as possible.  
I ran into a roadblock changing configuration of CoreGen devices, so
was simply going to force the eventual user to go through the GUI
for any modifications.  Then I RTFM.  ;-)

In the Comparator V9.0 Product Specification there an example of
direct instantiation (Page 7), which looks like it'll save me a lot
of headaches.  I can simply use the generics I already have to
manipulate the core.  My problem is that ISE doesn't find the
comparator in the library.  I've had the problem (with ModelSim)
where the libraries change and I'm pointing to an old copy but I
don't know where to tell ISE where the libraries are.  I've always
used the GUI to generate cores before, but I really like the idea of
direct instantiation.  I can make my designs far more flexible
without a whole lot of work.  Anyone with a cluestick?


Re: Xilinx LogicCore Direct Instantiation
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Any reason to not just infer the comparator?  VHDL generics make this
sort of thing a breeze.

Rob Gaddi, Highland Technology
Email address is currently out of order

Re: Xilinx LogicCore Direct Instantiation
snipped-for-privacy@technologyhighland.com says...
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Two things...  First, I want to walk before running.  I also need to
manually instantiate BRAMs and it would be nice to ditch the GUI
altogether.  It would make managing mu libraries through various
core releases much simpler.  

Perhaps it's no longer true, but I found that the LogicCore devices  
were better optimized than the ones that were inferred from HDL.  
For equality, I'd just infer the thing and be done with it.  Long
magnitude comparators can have significant delays.  At least that's
what I've found in the past.  (UPDATE: I did a test and inferred the
comparators and one level up, even and it still seemed to pass
timing (10% buffer through PAR) with the widest compare I expect (32
bits).  Perhaps I'll go this way for the comparator anyway.  It's

I don't need generic for the inferred comparator (other than the
ones describing the busses that are already there).  ;-)


Re: Xilinx LogicCore Direct Instantiation

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IMO it is good practice to infer first, while bearing this statement in
mind. Then you have a portable design which may be largely good enough;
you only need to pay attention to instantiation where the inferred
design fails size or timing (which does still happen sometimes)

Sounds as if the comparators are good enough now.

- Brian

Re: Xilinx LogicCore Direct Instantiation
brian snipped-for-privacy@btconnect.com says...
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Perhaps, but I never know what will be asked next (portability will
not).  I'd like to have as robust of a design as possible out of the
box, since I won't be around to pick up the pieces.

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The comparators are good enough and I think I know how to make them
faster, if need be.  This doesn't do the BRAMs any good though.  
They're still going to be a PITA.


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