Xilinx EDK and reference system opb_ssp1_v1_00_a

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Hy all!

Since an view days I am using the EDK 6.1i from Xilinx. Now I tried to
use their reference design "opb_ssp1_v1_00_a". It's a design for the
Virtex II pro with an OPB-slave with interrupt support.

But when I try to generate the bitstream, I get an error like this:

- Running XST synthesis
opb_core_ssp1_wrapper (opb_core_ssp1) -
X:\v2p\opb_ssp1_v1_00_a\system.mhs:243 -
Running XST synthesis
ERROR:Xst:807 -
line 189: arguments of 'and' operator must have sa
me lengths.
ERROR:MDT - HDL synthesis failed!
ERROR:MDT - platgen failed with errors!

Hm, I am not very familiar with VHDL and the EDK and I have no idea
what to do!

Thank you -


Re: Xilinx EDK and reference system opb_ssp1_v1_00_a
Please submit your MHS to xilinx support.

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