Hello
I am using Synopsys fc2_shell and the Xilinx ISE 6.1 Tools to creat
my FPGA-Design. When I define a clock frequency (like 20 MHz) Synopsys generates a edif-netlist. After using ngdbuild i get a UCF-File which contains a constraint like "max. PAD TO PA Delay=50ns" (Syntax is quite different)
My Question is: If I use registered Multipliers, Adders, etc. I wan
to have a Register to Register constraint defined because the Desig itself is allowed to take more than one clock cycle for calculation How can I do this? Does anybody know how to define this
Thank you
parit