SRLen7 : SRL16 -- synthesis translate_off generic map( INIT => x"0000") -- synthesis translate_on port map (Q => enadd5_d4, A0 => '1', A1 => '1', A2 => '0', A3 => '0', CLK => clock, D => enadd5);
PROCESS(clock,reset) begin if reset ='1' then BITVECTOR4 '0'); EVECTOR4 '0'); elsif clock'event and clock ='1' then
if equal9='1' and enadd5_d4='1' then BITVECTOR4 enadd5_d3, A0 => '0', -- changed from 1 to 0 A1 => '1', A2 => '0', A3 =>
'0', CLK => clock, D => enadd5);
PROCESS(clock,reset) begin if reset ='1' then BITVECTOR4 '0'); EVECTOR4 '0'); enadd5_d4