I am using virtes II pro pci card .The card has a pci bridge with a bus linking processor in the bridge to the fpga. The constraints on the processor bus signals were givent by the vendor. My design gives me a negative slack on 2 of the signals on the processor bus. Will this affect the design ? I am doing dma from the fpga to the host RAM along the bus. The transfer rate is low. I was googling for links to read on negative slacks but could not find good ones for a starter. Thanks,
-D