Spartan-6 66mhz pci

I'm trying to make a simple PCI interface in a XC6SLX45. In the end I'll probably go with the premade Xilinx core but I wanted to get familiar with the details first. It seems that the chip simply cannot meet the timing for this under any circumstances. I've use the UCF pinouts created for the xilinx core hoping this includes some magic. Creating a simple do nothing design that essentially registers frame_n and pipes it out of trdy_n using a BUFIO2 clock i was able to achieve this:

Slack (slowest paths): -0.671ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: Inst_pci_wrapped/pci_trdy_o_int (FF) Destination: TRDY_N (PAD) Source Clock: clk_buf rising at 0.000ns Requirement: 7.000ns Data Path Delay: 4.597ns (Levels of Logic = 1) Clock Path Delay: 3.049ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns

Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2

• PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns

Maximum Clock Path at Slow Process Corner: PCLK to Inst_pci_wrapped/ pci_trdy_o_int Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- L4.I Tiopi 1.040 PCLK PCLK PCLK_IBUF ProtoComp8.IMUX.12 BUFIO2_X1Y15.I net (fanout=1) 0.413 PCLK_IBUF BUFIO2_X1Y15.IOCLK Tbufcko_IOCLK 0.096 bufio2_inst bufio2_inst OLOGIC_X0Y59.CLK0 net (fanout=2) 1.500 clk_buf -------------------------------------------------

--------------------------- Total 3.049ns (1.136ns logic, 1.913ns route) (37.3% logic,

Maximum Data Path at Slow Process Corner: Inst_pci_wrapped/ pci_trdy_o_int to TRDY_N Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- OLOGIC_X0Y59.OQ Tockq 0.842 Inst_pci_wrapped/pci_trdy_o_int Inst_pci_wrapped/pci_trdy_o_int M3.O net (fanout=1) 0.234 Inst_pci_wrapped/pci_trdy_o_int M3.PAD Tioop 3.521 TRDY_N Inst_pci_wrapped/trdy_buf_inst/OBUFT TRDY_N -------------------------------------------------

--------------------------- Total 4.597ns (4.363ns logic, 0.234ns route) (94.9% logic,

It seems unlikely to me that any of that can be removed, and it is not even close to the 6ns clock to out that I need. Am I missing something? How can 66mhz pci timing possibly be met in a device with