I used a PLX chip a few years ago and had very little trouble with it. PCI was not so easy to learn, but otherwise it was no big issue. I would recommend that you use a PCI bus analyzer to help you debug your low level protocol. Or you might not need it if you are doing a simple memory mapped interface. We were doing DMA and needed all the help we could get since we didn't have much info on the disk controller bus master.
Rick "rickman" Collins
Personally I prefer using a separate chip because it allows me to load that FPGA through the PCI bus making field upgrades easy. I am waiting with putting PCI inside of a FPGA until modular design and partial reconfiguration will allow me to achieve the same level of flexibility.
I've used PLX 9030 and 9656 in different designs, and they're actually pretty easy to use. The local bus is fairly straightforward. I don't think they have Verilog or VHDL models of their local bus. I did write my own, based on the data sheets, and it matched the real hardware (always a bonus).
I also did a design with the QuickLogic QL5064. The local bus (inside the FPGA) is also fairly straightforward and their simulation models are correct. It's also fast -- I set up a DMA test from one QL5064 (as a master) to another (as a slave) behind a bridge and I got damn near max PCI64/66 bandwidth. The main downside to the part (other than its expense -- $110 a pop) is that it's an OTP BGA, so you'll need to use a fairly expensive socket and be prepared to burn through a bunch of chips.
My current design is based on a roll-my-own PCI interface in an FPGA, for two reasons: 1) no room on the board for a PLX (or other) controller chip), and 2) my application requires a DMA engine that I don't think maps too well to Brand A or Brand X's IP.
I will also say that a PCI bus analyzer is mandatory.
I wasn't trying to push for or against the PLX type approach. Just pointing out that there are ways to change the configuration when your design gets loaded from a PROM. Board space or layour or something else might make the PLX/bridge unattractive.
Another potential disadvantage of the PLX/Bridge is a few more clock cycles if you just want to do a simple read. (Writes can be pipelined.)
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The design I worked on used a small CPLD along with the PLX chip and allowed the download to come from the main CPU with no PROM. This was used to download different configurations for different modes of operation (selftest vs. record vs. playback).
Rick "rickman" Collins