a question in the pci interface design

Hi,friends I am designing a pci target interface with cpld. And I want to meet the

66Mhz pci timing requirement with lattice's ispMACH 4256V-5 (Tpd=5ns). It seems that it is hard to meet the Tsu (
Reply to
rat
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Hi,

There are some enhancements in the architecture that make the ispMACH better than the Max7k (or Max3k).

  1. Have you tried the ispExplorer in the ispLEVER software? This tool gives you the opportunity to optimize your design and make a comparison between different settings.
  2. Study the architecture and make use of it.
  3. work with your local FAE to find a solution, he will be able to judge the settings and the design.

Best regards

Reply to
Luc Braeckman

Hi,

I do not believe it is possible to register all the PCI inputs, nor the IRDY signal, for PCI. I've never seen anyone do this. Every PCI core I've ever seen has logic between many pins and the first bank of registers, and IRDY and TRDY are two of the critical signals given their high fanout. This does result in very tight Tsu timing, but that's fundamental to the standard.

The MAX 7000A family is not 66 MHz PCI compliant. To get to 66 MHz, you have to use the faster MAX 7000B family.

Vaughn Altera

Reply to
Vaughn Betz

Hi

Our PCI target core registers every signal, IRDY and TRDY too. It works greatly, and it was used in about 11 commercial products.

Regards, Laurent Gauch

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Reply to
www.amontec.com

register FRAME, too?

Reply to
rat

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