realize pci in fpga

Cyclone is not compatible with PCI 5v, the voltage transients exceed 5v and will damage the device.

You will need to use IDT Quickswitch or similar device to limit the input voltage to your Cyclone in a 5v scenario.

Google for PCI and quickswitch, you should find a Xilinx app's note on the subject.

Alan

... or look a the schematics for the Altera Cyclone PCI development kits.

-hpa

Finding is better than looking....

ftp://ftp.altera.com/outgoing/devkit/PCI_DK_2C35/schem_cii_pcidevbd_b.pdf

Karl.

Thanks all.

risistors.

Can somebody help me to solve the first question?

Making the clock track longer gives you better setup but reduces your hold time on data getting written to your chip.

For reads from your chip (or DMA writes), you have to make sure your clock to out timings allow for two types of extra delay. First is getting through the bus switch. Second is the extra delay because your clock is late because it is going through the bus switch on the way in.