Relative placement constraints in VHDL for Virtex multipliers

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I often have timing problems when using virtex-II dedicated
multipliers. After synthesis/P&R I have fixed these by looking at the
placement with ISE floorplanner and then constraining the multipliers
and their i/o registers to be packed as close together as possible.
This requires too much effort for this lazy engineer. I must be
possible to do this constraining in my VHDL code via attributes. How?
Does anyone have a bit of example code?

I don't really want to place the multiplier in any certain spot,
rather just make sure that the registers holding its input and
catching its output will be placed in the adjacent slices...

Thanks in advance for your help.

Re: Relative placement constraints in VHDL for Virtex multipliers
Jack,
http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp

Relationally Placed Macros

          HTH, Syms.

snipped-for-privacy@hotmail.com (Jack Stone) wrote in message
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