Attention all gurus,

I have a general question regarding constraints and asynchronous interfaces. How do you specify details like "offset in before" when you really have no idea when the signals will be arriving. I ask only because I have an asynchronous interface that I need to get working at a higher frequency and I feel that the only problem lies in the fact that I can't tell the tools that I need this block to meet certain speeds using constraints. I'm new at the constraints aspect of things other than using the basic "period" constraint.

Details are: Asynchronous device is a uP running at 40 MHz, I have a set of read/write 32 registers (32 bits wide) that are setup in the FPGA (Spartan II xc2s150 device speed rating is a 5) running at 100 MHz. All transfers where the uP reads from the registers are working perfectly, however the occasional write transfer is not (maybe 1 out of 50 on average). Chip select, write, read, address, and data lines are all the lines that I have available.



jberringer at the domain sympatico dot ca

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Jason Berringer
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have no

frequency and


new at

If the input signal is not synchronous to the clock, no constraint will effectively handle the sampling for you. You need to assume that the input can create setup or hold time violations at some transitions. The important thing is to design your logic to handle cases where the signal falls in the forbidden window. The first rule to observe when you sample an asynchronous signal is to sample it in only one place. This means, for example using an IOB input flip-flop to sample the signal once, and to only use the Q of that flip flop for any internal decision. If you don't do this, some parts of your logic may see the input signal high on a particular clock edge while others see it low on the same edge. I suspect this is what is happening when writes don't work. Note again that no constraint will fix this, you need to design for it. For example:

reg in_ff; ref in_dly; always @ (posedge clk) in_ff

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