Attention all gurus,
I have a general question regarding constraints and asynchronous interfaces. How do you specify details like "offset in before" when you really have no idea when the signals will be arriving. I ask only because I have an asynchronous interface that I need to get working at a higher frequency and I feel that the only problem lies in the fact that I can't tell the tools that I need this block to meet certain speeds using constraints. I'm new at the constraints aspect of things other than using the basic "period" constraint.
Details are: Asynchronous device is a uP running at 40 MHz, I have a set of read/write 32 registers (32 bits wide) that are setup in the FPGA (Spartan II xc2s150 device speed rating is a 5) running at 100 MHz. All transfers where the uP reads from the registers are working perfectly, however the occasional write transfer is not (maybe 1 out of 50 on average). Chip select, write, read, address, and data lines are all the lines that I have available.
jberringer at the domain sympatico dot ca