Hello Group.
Not being that familiar with Altera's Quartus II, and it may be a beginners problem... Anyways... I'm compiling a VHDL-based design for the MAX-II EPM1270F256C5, which Ifinally managed to get error-free. When trying to back-annotate the Fitter's suggestion for the pin placing, the Pin Planner's list section actaully states two entries for the same physical pin and signal like this:
mpifdX[7] PIN_J14 mpifdX[7]~0 PIN_J14
I have run the Remove Assignments before the Back-annotation The signals giving this problem are always and ONLY the bidir's.
- Has anyone seen something similar and can give an explanation...?
Thanks i advance.
Jesper.