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Partial Reconfiguration

Hi all, I am interested in doing partial reconfiguration using Xilinx Virtex

2 pro, i am having a HW AFX xilinx prototype baord. I tried the small bit manipulation method defined in Xilinx application note xapp290, with the simple example , Example 1 simple system desing from xilinx EDK examples web page. Ok , my desing is this, I am using PPC405, and uartlite and gpio with uart continiously writing some data in Hyper terminal and gpio is connected to four leds and writing '1' to it I tried to change the routing for the LEDs , I do have to mention here, my board has 8 user LEDS, i changed the routing from upper half to lower half and generated the partial bit stream. Everything goes well so far, but when i download this partial bitstream into FPGA, my uart stops putting out data, but LEDS gets rerouted and now the lower half LEDs o/p '1'. I would like to know wether what i am trying to do was right, also if anybody worked on small bit manipulations, I would appreciate their comments and advice. Thank you for the posting me a reply. bye Ram
Reply to
ram
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The configuration frames are columns, so if the routing you are changing is in the same column as the PPC, UART, or any of their routing, they will probably stop.

Steve

Reply to
Steve Lass

I am looking at using this feature, although not while the chip is running. One problem I foresee is that with a column alignment, a module might be very hard to route if it is restricted to just a small number of columns.

In my application there are 5 modules with one being constant and four being changed according to the hardware that is connected. Some of the planned modules are much larger than others, so I don't see them mapping to a fixed footprint. Some may be as narrow as two or even one column in an XC3S400.

So I have been thinking about partitioning the designs differently. Instead of mapping modules to columns, I would divide the columns in half and map the designs to half columns. This won't be an issue as long as none of the logic (or interconnect) in the column is being used by running circuitry. But it will require that the bit files be assembled from partial bit files. Each column will need to be made of two halves glued together. As long as there is no routing between them, this should be a simple matter of concatenating two separate streams for each column.

Anyone know if this might be practical?

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Rick "rickman" Collins

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Reply to
rickman

Anything is possible, but I wouldn't call it practical. There are no tools to help out with this type of methodology.

I'm not sure how many different combinations you have, but if it's a reaasonable amount, I would suggest creating bistreams for each combination. It seems like you have to do that anyway with your proposal.

Steve

Reply to
Steve Lass

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