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Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)

I have converted an old Xilinx schematic design into VHDL. However, I'm

running into a problem with how to implement the GSR function properly.

I'm used to having an external reset line feed one of the pins, that could be specified to Leonardo 4.22 as the global_sr signal. This design, however, used an internally generated pulse from the configuration section to pulse the registers.

When I try to read in the design, I get told by Leonardo that the GSR net name that I'm using does not have a source --> looking at the schematic viewer, I find that all of the GSR nets get grounded.

Any thoughts on how I can resolve this issue are welcomed. I'm going to review the older Leonardo documentation, as well as look at the Xilinx docs regarding the STARTUP block. (One of the things, however, is that the Leonardo docs state NOT to instantiate the BSCAN or STARTUP block -- which I'm not sure about).

Regards, Bob

Reply to
Bob Myers
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Actually, Leo will find the external reset and put it on a global line for you if you use a standard synchronous template.

Use of the GSR in your design description is optional and the Leo default is to not use it. I think this is a good thing as it makes your design more portable and easier to simulate.

Consider using an external pin for reset.

-- Mike Treseler

Reply to
Mike Treseler

The method I use in VHDL to implement the GSR is to instantiate within the design a ROC primitive (which is in the Xilinx unisim library). All of the Xilinx tools for many years have understood that this net is the GSR, and I would assume that Leonardo would too. ROC simply outputs a reset pulse of a few 100nS, just like the real GSR.

-- synthesis translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL;

-- synthesis translate_on

... component roc port ( O : out std_logic ); end component;

... roc_e: roc port map( O => RESET );

Reply to
Duane Clark

Duane;

Thanks for the info on ROC. I'm going to try it out; hopefully the synthesis tool and Xilinx M1.5i router will handle it (I'm using the tools "of the time").

I'll post later today, after I review the outputs of the two tools.

Regards, Bob

Duane Clark wrote:

Reply to
Bob Myers

This did the trick...in more than one way...

Thanks for the advise on using ROC (Reset On Configuration).

-Bob

Bob Myers wrote:

Reply to
Bob Myers

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