I've got some Spartan-3 IP from a vendor which uses a DCM. However, the DCM doesn't appear to be doing anything. The DCM is wired up as follows:
1) A global clock pin on the device drives signal CLK1, which goes into the IP block, where it connects to DCM/CLKIN . CLK1 is not used anywhere else in the design.2) DCM/CLK0 drives signal CLK2
3) signal CLK2 drives an instantiated BUFG, and comes out as CLK34) CLK3 is connected back to DCM/CLKFB
So far, so good; this is exactly the "On-chip with CLK0 feedback" setup shown in fig 15(a) on p23 of the datasheet (as an aside, 15(a) shows CLKIN coming from a BUFG, which doesn't seem to be correct in this case; it doesn't fit with the diagram on p30).
The problem is that none of the other outputs from the DCM are used: all the clock outputs, apart from CLK0, are open.
Now, I'm a bit rusty on Xilinx, but it seems to me that this DCM is doing nothing if the other clock outputs are unused. Is this correct? The DCM is set for 1X operation.
Some other info:
1) CLK3 drives all the logic in the IP block2) CLK3 is driven out of the IP block, and drives all my logic
3) My logic doesn't communicate with the IP, except via an asynchronous FIFO. The vendor expects my side of the FIFO to be driven with CLK3.TIA -
Rick