instantiation in verilog

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hi
i dont know how to make a top module and create instances of other
modules in it.

my top module is CHK
and other modules are BUFFER1, BUFFER2 and BUFFER3.

now i want to create their instances in my top module, moreover i want
to know what will be the format of the top module, as in what inputs
and outputs will i declare in it, (i/os of all the 3 modules or wat?)

this is my buffer1 module:



module buffer1(clk,a,led1,led2,sum,sum1,buff1a,buff1b);

input clk;
input a;

output led1;
output led2;
output [19:0] sum;
output [15:0] sum1;
output [127:0] buff1a;
output [127:0] buff1b;

parameter num1 = 15'hFFFF;

reg led1;
reg led2;
reg [19:0] sum;
reg [15:0] sum1;
reg [127:0] buff1a;
reg [127:0] buff1b;

always @(clk)
begin

if(a==1)
begin
buff1a = 127'hcda9005095209e7d0de2686650101032;
buff1b= 127'h1a6f0000c0a806f3453f602800060014;//correct packet
sum=
(buff1a[3:0]+buff1a[7:4]+buff1a[11:8]+buff1a[15:12]+buff1a[19:16]+buff1a[23:20]+buff1a[27:24]+buff1a[31:28]+buff1a[35:32]+buff1a[39:36]+buff1a[43:40]+buff1a[47:44]+buff1a[51:48]+buff1a[55:52]+buff1a[59:56]+buff1a[63:60]+buff1a[67:64]+buff1a[71:68]+buff1a[75:72]
 
+buff1a[79:76]+buff1a[83:80]+buff1a[87:84]+buff1a[91:88]+buff1a[95:92]+buff1a[99:96]+buff1a[103:100]+buff1a[107:104]+buff1a[111:108]+buff1a[115:112]+buff1a[119:116]+buff1a[123:120]+buff1a[127:124]+buff1b[3:0]+buff1b[7:4]+buff1b[11:8]+buff1b[15:12]+buff1b[19:16]+buff1b[23:20]+buff1b[27:24]+buff1b[31:28]+buff1b[35:32]+buff1b[39:36]+buff1b[43:40]+buff1b[47:44]+buff1b[51:48]+buff1b[55:52]+buff1b[59:56]+buff1b[63:60]+buff1b[67:64]+buff1b[71:68]+buff1b[75:72]
 
+buff1b[79:76]+buff1b[83:80]+buff1b[87:84]+buff1b[91:88]+buff1b[95:92]+buff1b[99:96]+buff1b[103:100]+buff1b[107:104]+buff1b[111:108]+buff1b[115:112]+buff1b[119:116]+buff1b[123:120]+buff1b[127:124]);
sum1= (sum[15:0]+sum[19:16]);

if(sum1==num1)
begin
led1=1;
end

else

led2=1;

end


this is buffer2:

module buffer2(clk,b,led1,led2,sum,sum1,buff1a,buff1b);

input clk;
input b;

output led1;
output led2;
output [19:0] sum;
output [15:0] sum1;
output [127:0] buff2a;
output [127:0] buff2b;

parameter num1 = 15'hFFFF;

reg led1;
reg led2;
reg [19:0] sum;
reg [15:0] sum1;
reg [127:0] buff2a;
reg [127:0] buff2b;

always @(clk)
begin

if(b==1)
begin
//buff2 =
255'hcda9005095209e7d0de26866501010321a7f0000c0a806f3453f602800060014;//
incorrect
buff2a= 127'hcda9005095209e7d0de2686650101032;
buff2b= 127'h1a7f0000c0a806f3453f602800060014;
sum=
(buff2a[3:0]+buff2a[7:4]+buff2a[11:8]+buff2a[15:12]+buff2a[19:16]+buff2a[23:20]+buff2a[27:24]+buff2a[31:28]+buff2a[35:32]+buff2a[39:36]+buff2a[43:40]+buff2a[47:44]+buff2a[51:48]+buff2a[55:52]+buff2a[59:56]+buff2a[63:60]+buff2a[67:64]+buff2a[71:68]+buff2a[75:72]
 
+buff2a[79:76]+buff2a[83:80]+buff2a[87:84]+buff2a[91:88]+buff2a[95:92]+buff2a[99:96]+buff2a[103:100]+buff2a[107:104]+buff2a[111:108]+buff2a[115:112]+buff2a[119:116]+buff2a[123:120]+buff2a[127:124]+buff2b[3:0]+buff2b[7:4]+buff2b[11:8]+buff2b[15:12]+buff2b[19:16]+buff2b[23:20]+buff2b[27:24]+buff2b[31:28]+buff2b[35:32]+buff2b[39:36]+buff2b[43:40]+buff2b[47:44]+buff2b[51:48]+buff2b[55:52]+buff2b[59:56]+buff2b[63:60]+buff2b[67:64]+buff2b[71:68]+buff2b[75:72]
 
+buff2b[79:76]+buff2b[83:80]+buff2b[87:84]+buff2b[91:88]+buff2b[95:92]+buff2b[99:96]+buff2b[103:100]+buff2b[107:104]+buff2b[111:108]+buff2b[115:112]+buff2b[119:116]+buff2b[123:120]+buff2b[127:124]);
sum1= (sum[15:0]+sum[19:16]);

if(sum1==num1)
begin
led1=1;
end
else
led2=1;

end

endmodule


this is buffer3 module:

module buffer3(clk,c,led1,led2,sum,sum1,buff3a,buff3b);

input clk;
input c;

output led1;
output led2;
output [19:0] sum;
output [15:0] sum1;
output [127:0] buff3a;
output [127:0] buff3b;

parameter num1 = 15'hFFFF;

reg led1;
reg led2;
reg [19:0] sum;
reg [15:0] sum1;
reg [127:0] buff3a;
reg [127:0] buff3b;

always @(clk)
begin

if(c==1)
begin
buff3a = 127'h0050cda90de2b8b695209e7e5010005c;
 //correct
buff3b 12%7'h2a440000453fb028c0a806f300060014;
sum=
(buff3a[3:0]+buff3a[7:4]+buff3a[11:8]+buff3a[15:12]+buff3a[19:16]+buff3a[23:20]+buff3a[27:24]+buff3a[31:28]+buff3a[35:32]+buff3a[39:36]+buff3a[43:40]+buff3a[47:44]+buff3a[51:48]+buff3a[55:52]+buff3a[59:56]+buff3a[63:60]+buff3a[67:64]+buff3a[71:68]+buff3a[75:72]
 
+buff3a[79:76]+buff3a[83:80]+buff3a[87:84]+buff3a[91:88]+buff3a[95:92]+buff3a[99:96]+buff3a[103:100]+buff3a[107:104]+buff3a[111:108]+buff3a[115:112]+buff3a[119:116]+buff3a[123:120]+buff3a[127:124]+buff3b[3:0]+buff3b[7:4]+buff3b[11:8]+buff3b[15:12]+buff3b[19:16]+buff3b[23:20]+buff3b[27:24]+buff3b[31:28]+buff3b[35:32]+buff3b[39:36]+buff3b[43:40]+buff3b[47:44]+buff3b[51:48]+buff3b[55:52]+buff3b[59:56]+buff3b[63:60]+buff3b[67:64]+buff3b[71:68]+buff3b[75:72]
 
+buff3b[79:76]+buff3b[83:80]+buff3b[87:84]+buff3b[91:88]+buff3b[95:92]+buff3b[99:96]+buff3b[103:100]+buff3b[107:104]+buff3b[111:108]+buff3b[115:112]+buff3b[119:116]+buff3b[123:120]+buff3b[127:124]);
sum1= (sum[15:0]+sum[19:16]);
if(sum1==num1)
begin
led1=1;
end
else
led2=1;

end

endmodule


now i just want to create the instances in the top module thats it so
what would be the code like?

module chk()

i want to know the syntax n all


endmodule




thanks

Re: instantiation in verilog
On Sat, 19 Jul 2008 08:48:42 -0700 (PDT), Ambreen Ashfaq Afridi

Quoted text here. Click to load it

This is quite easy. Port connections are similar to wires which means
you have declare busses of the same width at the higher level and
connect them to your ports. For inputs (to lower level modules) the
wires should be coming from inputs directly or from drivers at the
same level ie:

module CHK(input tclk, input ta, output tled, output [19:0] tsum,
...);

wire [19:0] tsum = ta ? sum1 : sum2;
wiire [19:0] sum1;

wire tled = ta ? led11 : led21;

buffer1 ubuf1(.clk(tclk), .a(ta), .led1(led11), .sum(sum1),...);

buffer2 ubuf2(.clk(tclk), .a(ta), .led1(tled21), .sum(sum2),...);

endmodule

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