In order to double my input clock of 48 MHz, I'm using a CLKDLL. I understand that I have to add a timing constraint so the synthesizer knows what frequency I'm operating at. I added the following to my .ucf file:
NET "clk48" TNM_NET = "clk48"; TIMESPEC "TS_clk48" = PERIOD "clk48" 48 MHz HIGH 50 %; NET "clk96" TNM_NET = "clk96"; TIMESPEC "TS_clk96" = PERIOD "clk96" "TS_clk48" / 2;
However, ngdbuild gives an error saying "clk96" could not be found in the design. Xilinx' support page
tells me to check if the name is the same as in the top-level netlist, which seems to be implementation/system.ngc, and is a binary file.
Which is the source file where my "clk96" should be mentioned, and do I have to do something more to get it there? Right now, clk96 is only a signal in one of my VHDL architectures.
Thanks Heiko