Hello,
I realized a design with two Microblaze with XPS 6.1, in a Virtex II-pro. The two processors are independant, execpt for the clock and reset signals. This design works well. My aim is to separate nom the two microblazes in distinct VHDL entities. Thus I exported the design in Projnav, creating a top-level entity ("stub") and a sub-module containing all the wrappers. All that is generated by XPS. If I program it without changing anything, it works.
Then I created a new VHDL entity and copied all that concerned the second Microblaze in that new entity. The implementation reports no problems, but on the FPGA; it doesn't work. Then I tried something simpler: to delete the second processor from the design, but it doesn't work either.
I think maybe there is a memory allocation problem, I don't really know how to deal with the BMM files in that case. Or maybe ISE 6.1 doesn't support a two-microblaze architecture???
Amaury Anciaux