I'm trying to build a system with Xilinx EDK 3.2 which will have 2 Microblaze processors running separate code on a Virtex-II (xc2v-1000).
In XPS, each microblaze component is attached to it's own data and instruction LMB's which have BRAM and BRAM controller blocks attached in turn. When I attempt to generate the bitstream, the process fails during the map stage. I get the following error message:
ERROR:Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. . . . Number of bonded IOBs: 132 out of 172 76% Number of Tbufs: 1 out of 2,560 1% Number of Block RAMs: 64 out of 40 160% (OVERMAPPED) Number of MULT18X18s: 6 out of 40 15% Number of GCLKs: 1 out of 16 6%
So it looks to me like the number of block RAM's is where the problem is. In the properties for each block ram, I've set the following properties: C_MEMSIZE = 8192 C_PORT_AWIDTH = 13
There is a total of 64k of block RAM available, so I figured that allocating 8k to each processor should be fine.
If anyone has tried something similar I'd appreciate some ideas.
Thanks in advance,