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DDR2 SRAM Stratix II questions

I posted this last week, but it has yet to show up on google groups, so I fear my news server isn't as healthy as I would like. So I apologize if this gets double posted.

I'm involved with a project where we are trying to figure out if a Stratix II will work for us. Our big question mark right now is memory. We would really like to use a DDR2 SRAM (for reasons I don't want to go into), but Mega-core doesn't support it. We're not opposed to building our own interface, but we're trying to understand the possible reasons Altera doesn't support it. We've been told that basically there's just no demand, so that's why it's not there, but we fear that's not the whole story.

First, we're very concerned about simultaneous switching outputs / noise. I'm not familiar enough with Quartus to determine if there is an SSO calculator (like there is in ISE). We need to hang several memory banks off a single part at 200 MHz, so this is a big concern.

Second, is the 1.8V HSTL driver in the Altera part capable of supporting the bi-directional specs of a DDR2 SRAM at 200 MHz. I'm sure that this answer is buried somewhere in the Stratix docs, but so far I have been unsuccessful in uncovering it - any help here?

Thanks, Eric Amundsen Special Purpose Processor Development Group Mayo Foundation, Rochester MN 507-538-5457; Fax 507-284-9171

Reply to
eric.amundsen
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If time is an issue, buy standard interfaces.

-- Mike Treseler

Reply to
Mike Treseler

SRAM != SDRAM :-)

Tommy

Reply to
Tommy Thorn

The Stratix II supports DDR2 as an interface to the NIOS2 processor, as indicated in the document pointed to by the link. You didn't indicate wether or not you were intending to use the NIOS2 or if you simply wanted to implement a DDR2 controller in the Stratix for connection to another processor. I would recommend tracking down an Altera FAE or seeing if there is a direct Altera application engineer in your area that can pay you a visit.

As far as cores go, another place to look is at "open cores" (.org I think it is). I believe they provide cores that you can download and use free of charge. I am not sure what their URL is though.

Reply to
Noway2

First, this is not being used with a NIOS2 processor, or any other type of processor. Basically need memory hanging off of a data path for data dependent storage/retrieval.

Second, we've been working with our FAE, but so far have basically been told, with respect to our memory issues, that since DDR2 SRAM is so rarely used we're pretty much on our own. We're trying to get some third party design services on board to help us out here, but those wheels slowly.

I will poke around open cores.

Eric

Reply to
eric.amundsen

Perhaps you should at least base your reply on the title of the document instead of the name of the link....or even better on more than just the title.

In any case, Altera's MegaCore (see link above) supports both DDR and DDR2 memories. I'm kind of missing why the original poster is not seeing this as well.

KJ

Reply to
KJ

Yes but the link is for SDRAM (Synchronous Dynamic RAM) while the O.P. asked about SRAM (Static RAM)

Sylvain

Reply to
Sylvain Munaut

We would really like to use a DDR2 SRAM (for reasons I don't want to go into), but Mega-core doesn't support it

There is no such thing as DDR2 SRAM which implies that the original post had a typo. Given that the most likely explanation is that the original poster meant to type 'DDR2 SDRAM' and not 'SRAM' as you have surmised.

KJ

Reply to
KJ

Look at this:

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;-)

Thomas

Reply to
Thomas Entner

I stand corrected.

Although I must admit that if all we're talking about is a synchronous SRAM controller then that is almost trivial to put together for oneself....to the point that I wouldn't let the lack of an Altera MegaCore function deter me from using the part if that's what one has in mind. Take an hour or two and write the code.

KJ

Reply to
KJ

Ignore my previous post...I re-read the original post...time to stop and put brain back in.

KJ

Reply to
KJ

and at this

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Reply to
John

"KJ" schrieb im Newsbeitrag news: snipped-for-privacy@m79g2000cwm.googlegroups.com...

Now I have re-read the original post again, too ;-)

Maybe one conclusion could be, that "no demand" is quite plausible, as you did not even believe they exist.

Regarding the bus-turnaround-time, which was one of the concerns of the OP, I think, I would recommend following:

Make a test-cirucit with the bi-dir DDR-IO-registers in Quartus and look what the timing-analyzer reports. I suppose that you will need 1 or 2 "wait-states" for bus turn-around.

Thomas

Reply to
Thomas Entner

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