Stratix 2 ALUT architecture patented ?

Lenz,

I am sure that they have filed for their patents. Since it takes two or more years, we will just have to wait and see what it is that gets patented.

How this is any different than f5/f6/f7/f8 muxes is also at issue: have they just "renamed" an already existing architecture? Do they now achieve the same packing that is already enjoyed by others?

Austin

Austin,

As a general rule, Altera likes to avoid using this site as a marketing tool. Instead, we choose to focus just on relevant technical questions. However, since you brought it up, the question at hand: is the innovation in Stratix II just a renaming of the f5/f6/f7/f8 muxes in Virtex products?

On the contrary, the Stratix II architecture represents a complete redesign of a programmable logic fabric.

Recognizing the need for a more powerful and efficient approach than the 4LUT + register fabric that all mainstream FPGAs have relied on for years, Altera increased the capability and flexibility of the Stratix II logic with a larger and truly adaptive logic module (ALM). An ALM can efficiently implement one to two 6LUTs, any 5LUT and 3LUT combination, two 5LUTs (for almost any 2 functions), any two 4LUTs etc...all in a single logic block. (For more complete listing, look here:

Previous FPGA architectures have only had 4LUT capabilities without routing between multiple logic blocks.

Virtex devices are really a 4LUT architecture with some MUXes (note that "variable LUT terminology" was only recently mentioned in a white paper but is not found in the data sheet). The f5/fX muxes are one way to emulate larger LUT functions, but this approach comes at the cost of multiple LC resources, routing structures between those LC's, and requires that the synthesis tool (or the designer) intelligently map to those muxes. Analysis of synthesis and place and route results, suggests the f5/fX resources are commonly used in large distributed memory functions and wide muxes, but rarely benefit wide LUT functions.

Comparing results of how real designs synthesize and map to Stratix II ALMs vs. Virtex-II Pro slices (the most direct comparison since each ALM/slice is capable of 2 4LUT functions) shows a 54% efficiency advantage for Stratix II. This increased logic efficiency also results in better performance and lower power, since with more logic density inside each logic block, less routing circuitry is used which tends to be slower and leakier by comparison.

For those of you curious to find out more details on this, the following white paper and web seminar may interest you:.

Logic Structure Comparison Between Stratix & Virtex-Based Architectures

Mike Rather Altera Corp.

Michael, Since you popped your head over the parapet... :)

What's the story on MAX II Devices ?. There was glossary, timing and lib files gradually appearing, and suddenly the Altera web is cleansed and it's like MAX II is now 'off the radar' ?. Would seem to indicate some problems.....

-jg

Michael,

Thank you very much. I have read all of the publicly available materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite leary of. For example, if the claim of a St2 50% speed improvement is really true, then our demonstrated 40% speed improvement on average in the i6.2 release makes St2 only 10% faster than our 2 year old V2 Pro.....lowest speed grade. So leaving marketing to those who enjoy it, I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box differently around the components. I am still puzzled, but the block diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it was actually designed this way then that is simply what it is. A true 6 LUT has 64 memory cells and the associated logic, and two of these seems a bit excessive and would not require any other logic or muxes at all. Combining existing 4 LUTs to deliver some of the possible terms of a 6 LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new architecture, as there are so many that now dot the landscape as dead skeletons of past FPGAs.

Austin

Hi Jim:

Rest assured there are no problems. The

site was refreshed; what you are experiencing is "housecleaning" on the site. MAX II data, lib files and documentation will be posted on altera.com when the product is launched - stay tuned.

Luanne Schirrmeister

-Altera

I can understand why. The way that Xilinx twists facts in their data sheets would certainly lead them to expect that of everyone. Just how many LCs *do* your parts have???

What kind of gobbledygook is that? Correct me if I am wrong, but your V2 is the newest and fastest parts you have, right? Certanly you can't tout the Spartan 3 since not many people have even seen them and they are much slower than most people would have expected given a 90 nm process.

And exactly how do you get a 40% speed advantage over anything with your software? Do you have benchmarks to back that up?

I don't follow this. Are you saying their approach is good or bad? If you are saying it is good, then you are agreeing with them. If you are saying it is bad, aren't you also saying it is just like yours? I guess the patents will tell all.

Yes, and some of those are in a unmarked grave out behind your facility, no? What was that company name... was it Plus Logic? How about NeoCAD? What are the others... ?

Guy?

Comments below.

google_guy wrote:

Easy, just look at how many LUTs there are in the data sheet. You can inflate the naw numbers any way you like, as opposed to using our "rules."

V2Pro is the latest production avaliable offering in 130 nm.

By being more clever than we were one year ago. Do you have benchmarks to back that up? Yes. Contyact your FAE and they will be delighted to show you the benchmarks of over 200 large actual customer designs that we have in our tool test suite.

Neither. It just looked at first glance that they had some muxes (just like we do). That they have a more direct LUT/MUX/LUT path which is faster may be true, and that would be good.

Hey, what is wrong with that? Yes, it is good. If you

Yes. What was that company name... was it Plus Logic? How

I will let you tell us.

Austin,

Our data contradicts the performance claims you are making, but this is not the right forum to argue back and forth about it.

Let's let the engineers and the market decide which claims to be leary of.

Best Regards, Mike

Michael,

True. All I pointed out is that the ALM architecture is a clear improvement (for Altera) and (if) it also has speed benefits, then that is even better.

A clear case of agreement.

I also mentioned that I don't believe your claims, and even if I did, we now claim a 40% improvement.

You don't believe my claim, so we are even again. Scarey if we agree too much....

So, here is the challenge: anyone who can actually do a design in both, and then let us know how well it behaves? Of course, no one is likely to believe just one design (as Peter notes), so the more who submit, the merrier (and the more believable it would be).

I would only leave as a last note that this is a comparison of the Virtex II Pro (two years old 0.13u) with the St2 (90 nm which isn't even sampling yet).

Austin

I don't like the nasty tone by that anonymous coward "google_guy" . But regarding the graves that Austin referred to, they are from: Intel, Motorola, Texas Instrument, AMD, Lucent, National Semi, and lots of lesser players.

Let's stop the bickering and concentrate on the fascinating technical possibilities offered by the new crops of FPGAs. Leave the mudslinging to the marketing folks. They are better trained in it, and they can tell the wildest stories with a straight face, without blushing. Let us be engineers. :-) Peter Alfke

Peter writes

Quote from Mark Twain follows:

"Rumors of my untimely demise have been greatly exaggerated."

might not be exact, but you get what I mean.

This is a terrific newsgroup. I know I have learned a fair amount about the topic while perusing the posts.

But let's remember, AMD's PLD business isn't dead, nor is Lucent's - although they BOTH now say LATTICE on the package. ;-)

Michael Thomas LSC SFAE New York/New Jersey

631-874-4968 fax 631-874-4977 snipped-for-privacy@latticesemi.com for the latest info on Lattice products - LATTICE - BRINGING THE BEST TOGETHER

How about Xilinx actually publishes the *real* numbers? If you inflate the numbers, of course you would expect your competition to inflate their numbers.

So what would you have Altera compare their products to, your V3 chips that you won't have out next year?

So your chips are not any faster, you have just figured out how to get the speed out of your chips. If you want to compare software do that, but we are talking about the chips, aren't we?

So you don't understand what they are doing, but you had to open your mouth anyway. :)

Hey, it's your graveyard.

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Hi Ray,

As I said, (tried to say?) I'm sure many of the smart guys here like you could rig the results at will - big deal. But what if you didn't go to the trouble to make one or the other come out miles ahead? Would it not be interesting to see the results?

I think its clear people don't really care because they've made up their minds which they prefer. Choosing A or X probably pales in comparison to pushing more of your design onto *any* state of the art FPGA. That's where I am - basking in the amazement that my hardware is configurable, my pins are assignable and I can add as much parallel logic as required to meet performance.

Frankly, it would take a lot to steer me away from Altera and Nios because of the ease of use and the effort the company went to to get us going.

Ken

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That cuts both ways. I'm willing to tweak my designs to take advantage of the hardware. That can make a big difference.

Perhaps what we want is a nice clean reference design, and then see what happens if people try to tweak it to look better on a particular device. (That might make a good open cores project.)

But that puts us back to discussing what makes a good reference design. See Peter's comments about PREP. But maybe the FPGA world has matured enough by now that we could build complete (interesting) designs rather than replicating simple counters.

Would LUTs/MIPS for an x bit CPU be an interesting measure? Both vendors have mature CPU technology.

I like Ray's offer. Maybe one of the trade rags will take him up on it.

--
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I suspect if one does a dozen apps, not all DSP, but a general variety, and for clock freqs all over the range from 50 to 300Mhz, you would get wildly varying results for which is better even if X & A agreed on 2 roughly equal technologies. Just doing same in X devices produces variations due to different strengths of different families even if closely derived.

I am willing to put up my 300MHz cpu when it is complete but I suspect I already know the answer, just look up in specs for who has fastest DP BlockRam cycle and N (say 12,16) bit adder or 3 4bLUT equiv levels. But I'd be curious to know A results too.

johnjakson_usa_com

I'm specifically referring to the very HEAVY NIOS optimizations between 1.1 and 2.0 described in the talk at FPGA this year, on " A High Performance 32-bit ALU for Programmable Logic" by Peter Metzgen of Altera. (Sorry, don't have it online).

The talk/paper was all ABOUT architectural tweaks/modifications to get the ALU and other structures to be not only much smaller, but only 2 LUT stages per pipeline stage, and the reason for the large size reduction between 1.1 and 2.0. IT really was programmed down at the LE level, understanding tricks with the carry chain etc.

How much reoptimiation was needed for Stratix II?

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

I'll argue that 4 apps acn be fairly good (heck, I did in the past) for this comparison, if you choose them well.

AES: Memory/SBOxes, delay chains, LUTs

Smith/Waterman: 16 bit ALU systolic operations

Sythentic datapath: What does a generic microprocessor-ish datapath look like

Sythesized processor core: How do pushbutton hairballs behave.

But doing the first three right is still probbaly 1-3 weeks of billable time for Ray Andraka (and 2-6 months for lazy gradstudents like I was).

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu