While waiting for the next announcement.... perhaps some Xilinx person could answer these questions?
Crista Souza's and Ron Wilson's piece in EETimes says in the final paragraph:
The column-based approach means that IP companies that either license to Xilinx or want to be acquired will
**now have precise physical constraints for how to incorporate their IP into Xilinx FPGAs**. Initially, that will whittle down the field of qualified vendors, but ultimately it will result in higher-quality IP, analysts said.Whom should one contact to find out more about these precise physical constraints?
Will it require the IP companies to work with expensive ASIC design and verification software, or will there be some new software which has the parameters which the designers can use already set up for the base platform and taking into account these constraints?
Thanks
Shiraz.