Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: The Manifest Destiny of Computer Architectures
I am reading in but readers may have different ideas. Reminds me of stories about Russian processors that came with a 'bad instruction' list the way disk drives (used to) come with a bad blocks list....
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12 years ago
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Has anybody used IOB_DLY_ADJ with S(2:0) input?
Hi, I have a DDR input which every now and then gives me a nonfunctional implem= entation due to unlucky input data clocking. Thought I would try to use the= variable delay input elements with the S...
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12 years ago
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FPGA acceleration v.s. GPU acceleration
I was an FPGA engineer before and I think high performance computing based FPGA will lead to a bright future. However through my recently projects I found GPU will be more appropriate when there is a...
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12 years ago
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Hiring Engineers Colorado
Denver/Boulder, CO. This position is an ideal opportunity for a PCB layout engineer with a wide range of design experience in areas ranging from RF to high-speed circuit board layout. Responsibilities...
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12 years ago
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Lattice XP2 getting hot and/or reading 0's as JTAG ID
Hi I guess I am alone with the issue, but asking still :) board(s) working ok, FPGA in SDM mode. suddenly after some repramming FPGA 1) goes HOT, reads bad JTAG ID, can be restored to live by changing...
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12 years ago
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facing problem in creating ..BMM file with RAMB18X2
Hi, i usually do ROM merge using Data2mem, but this time my design use RAMB18x2 inside it they split it for RAMB18_Upper and RAMB18_Lower, but RAM instance remain same for both RAMB18_upper and...
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12 years ago
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reduce EDK synthesis time
Hello, i'm working on microblaze project (using ISE 10.1) and obviously adding peripheral the EDK synthesis takes a long time. There's a method or tool to improve this time?? I've tried the...
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12 years ago
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Altera Cyclone 4 deserialization, banks, pll
Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data and a...
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12 years ago
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interfacing Xilinx platform usb jtag with other vendor devices
is xilinx platform usb jtag supports non-xilinx devices regards salim --------------------------------------- Posted through Everything FPGA: Forums (including comp.arch.fpga), Blogs, WhitePapers,...
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12 years ago
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Xilinx ISE Design - XPS won't start
Hello everyone, Recently I installed Xilinx ISE Design Suit 13.1 for studying. I got the licence right and everything, but unfortunately I faced a few strange problems... First of all, I can't run all...
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12 years ago
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POST_CRC in Spartan-6
Hi all! Anyone tried using the post-configuration scrubbing function in Spartan-6? I am a little at a loss reading the documentation, so any first-hand experience would be valuable. From the...
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12 years ago
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Virtex-6 XC6VHX380T Master SPI Configuration Problems....
Hello Group. I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master SPI loading problem. Everything seems to go smoothely - Clock and Read command (0x03) is given and the PROM returns...
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12 years ago
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Re: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO standard in Virtex II Pro (XC2VP30, package ff896)
QtNTQ3Ny00YzUw... Y3Yi00MDFj... . n =3D NONE You need to explicitly state which board that you are using as there are many boards, from many vendors. When you reference pins of a connector (A20 to A27...
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12 years ago
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DSP power consumption in Virtex devices...
Hi All, I remember a while ago I read an article on Xilinx website regarding low power modes of DSP blocks and Block RAMs on newer virtex devices (V6 and V7 I guess). I know of suspend mode in Spartan...
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12 years ago
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A free lunch
The Python community is about to offer us a free lunch. A new compliant interpreter, pypy, is already 4.3x faster than cPython, and getting faster everyday. It shows that there is not conceptual...
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12 years ago
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