Latest threads in Field-Programmable Gate Arrays

Re: The Manifest Destiny of Computer Architectures

> At every computer conference I attend, I see numerous papers that show > how to incrementally increase the capabiliti...

46 15yrs

gah

46 15yrs gah

Has anybody used IOB_DLY_ADJ with S(2:0) input?

Hi, I have a DDR input which every now and then gives me a nonfunctional implem= entation due to unlucky input data clo...

1 15yrs

svenn.bjerkem

1 15yrs svenn.bjerkem

FPGA acceleration v.s. GPU acceleration

I was an FPGA engineer before and I think high performance computing based FPGA will lead to a bright future. However t...

7 15yrs

hitsx

7 15yrs hitsx

Hiring Engineers Colorado

Denver/Boulder, CO. This position is an ideal opportunity for a PCB layout engineer with a wide range of design experie...

2 15yrs

gaile.meeks

2 15yrs gaile.meeks

Lattice XP2 getting hot and/or reading 0's as JTAG ID

Hi I guess I am alone with the issue, but asking still :) board(s) working ok, FPGA in SDM mode. suddenly after some re...

6 15yrs

antti.lukats

6 15yrs antti.lukats

facing problem in creating ..BMM file with RAMB18X2

Hi, i usually do ROM merge using Data2mem, but this time my design use RAMB18x2 inside it they split it for RAMB18_Uppe...

1 15yrs

leeladhar.iitkgp

1 15yrs leeladhar.iitkgp

reduce EDK synthesis time

Hello, i'm working on microblaze project (using ISE 10.1) and obviously adding peripheral the EDK synthesis takes a lon...

4 15yrs

catto.15

4 15yrs catto.15

Altera Cyclone 4 deserialization, banks, pll

Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of t...

0 15yrs

oktem

0 15yrs oktem

interfacing Xilinx platform usb jtag with other vendor devices

is xilinx platform usb jtag supports non-xilinx devices regards salim --------------------------------------- Posted thr...

3 15yrs

a1234573

3 15yrs a1234573

Xilinx ISE Design - XPS won't start

Hello everyone, Recently I installed Xilinx ISE Design Suit 13.1 for studying. I got the licence right and everything,...

0 15yrs

zenmaster04

0 15yrs zenmaster04

POST_CRC in Spartan-6

Hi all! Anyone tried using the post-configuration scrubbing function in Spartan-6? I am a little at a loss reading the...

1 15yrs

noreply.larthe

1 15yrs noreply.larthe

Virtex-6 XC6VHX380T Master SPI Configuration Problems....

Hello Group. I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master SPI loading problem. Everything seems...

2 15yrs

repser66

2 15yrs repser66

Re: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO standard in Virtex II Pro (XC2VP30, package ff896)

> Hi, > I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit > parallel data from FPGA. The output fro...

2 15yrs

ed.mcgettigan

2 15yrs ed.mcgettigan

DSP power consumption in Virtex devices...

Hi All, I remember a while ago I read an article on Xilinx website regarding low power modes of DSP blocks and Block RA...

0 15yrs

amirhossein.gholamipour

0 15yrs amirhossein.gholamipour

A free lunch

The Python community is about to offer us a free lunch. A new compliant interpreter, pypy, is already 4.3x faster than...

5 15yrs

jan

5 15yrs jan

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