Virtex-6 XC6VHX380T Master SPI Configuration Problems....

Hello Group.

I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master SPI loading problem. Everything seems to go smoothely - Clock and Read command (0x03) is given and the PROM returns data to DIN... But loading never stops at the expected point, clock runs on and of course no Config or Done is reached....

Thus - simple question: Are there anybody here that have a working Master SPI loading of the Virtex-6 XC6VHX380T or similar devices in the same family?

Bit data come out of the ISE 13.2 BitGen tool, which have been found to suffer under this "feature":

-

Currently, we are using these options:

-w

-g DebugBitstream:No

-g CRC:Enable

-g ConfigRate:2

-g CclkPin:PullUp

-g M0Pin:PullUp

-g M1Pin:PullUp

-g M2Pin:PullUp

-g ProgPin:PullUp

-g InitPin:Pullup

-g CsPin:Pullup

-g DinPin:Pullup

-g BusyPin:Pullup

-g RdWrPin:Pullup

-g HswapenPin:PullUp

-g TckPin:PullUp

-g TdiPin:PullUp

-g TdoPin:PullUp

-g TmsPin:PullUp

-g Disable_JTAG:No

-g UnusedPin:PullDown

-g UserID:0xFFFFFFFF

-g ConfigFallback:Enable

-g BPI_page_size:1

-g OverTempPowerDown:Disable

-g next_config_addr:0x00000000

-g JTAG_SysMon:Enable

-g DCIUpdateMode:Quiet

-g StartUpClk:CClk

-g DONE_cycle:4

-g GTS_cycle:5

-g GWE_cycle:6

-g Match_cycle:Auto

-g Security:Level1

-g DonePipe:No

-g DriveDone:No

-g Binary:Yes

Are there anything else one should be focused on when setting the -g "options"...?

Thanks in advance for your time & best regards,

Jesper.