Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
pipelined algorithm, flow control
Hi, one RTL coding style for pipelined processing goes as follows: - set arguments to function with latency, i.e. memory lookup or multiplication - set a trigger bit (/multi-bit word) in a parallel...
2
|
10 years ago
|
2 | |
|
|
Parametrized, synthesizable FFT engine
Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length of FFT (as power of two), define the format of the numbers and adjust the engine...
1
|
10 years ago
|
1 | |
|
|
Verilog (Xilinx): Virtual tristate or muxes?
Hi, I've got some FPGA resources that are shared, for example RAM and multiplier. Instead of explicitly muxing the inputs, would it make sense to use "virtual" tristate ports in connected modules? I'd...
7
|
10 years ago
|
7 | |
|
|
PathFinder Source Code (in C)
Hi Guys, I am currently working on FPGA accelerators for PathFinder algorithm (FPGA routing algorithm). I am planning to use a HW/SW co-design to speedup the a lgorithm but I need a C code...
2
|
10 years ago
|
2 | |
|
|
Programming a Digilent S6 Carrier (Spartan 6
Hi, I'm programming the Flash memory in a Digilent "S6 carrier" board. It takes a long time, about 8 minutes. The configuration file size is 1484404 bytes and I'd expect it to take around 10s at a...
4
|
10 years ago
|
4 | |
|
|
XC9572-15PC84C - need to purchase
Hello All, I am looking to purchase up to 800 pieces of this Xilinx item: XC9572-15PC84C I can also use XC9572-15PC84I - lead free or leaded. If you have any excess inventory to sell, please contact...
—
|
10 years ago
|
— | |
|
|
XC9572-15PC84C
Hello All, I am looking to purchase up to 800 pieces of this Xilinx item: XC9572-15PC84C I can also use XC9572-15PC84I - lead free or leaded. If you have any excess inventory to sell, please contact...
—
|
10 years ago
|
— | |
|
|
chip-to-chip serial comms
What do you recommendation for serial communications between FPGA chips? We have one FPGA sending configuration information to multiple other FPGAs. T he FPGAs will be on different boards. The...
2
|
10 years ago
|
2 | |
|
|
my first microZed board
Just got this from production: from previously posted layout... This is a pretty serious signal processor application, but dropping the Zed on there makes it easy. We can plug a USB logic analyzer...
21
|
10 years ago
|
21 | |
|
|
Math is hard
Hey y'all -- So this is one of those times that my lack of serious math chops is coming round to bite me, and none of my usual books is helping me out. I'm hoping someone has some thoughts. I'm trying...
25
|
10 years ago
|
25 | |
|
|
embedded RAM vs. registers
Hi everyone, I'm trying to optimize the footprint of my firmware on the target device and I realize there are a lot of parameters which might be stored in the embedded RAM instead of dedicated...
10
|
10 years ago
|
10 | |
|
|
Xilinx Virtex-6HXT FPGA - XC6VHX565T-2FFG1923E - 27 pieces for sale
We have for sale 27 pieces of XC6VHX565T-2FFG1923E manufactured Xilinx/2013 date code - brand new original packaging. Please contact me with any interest. Thanks! Tiffanie Crocker E&O Analyst UniQuip...
—
|
10 years ago
|
— | |
|
|
EDA Playground
For those that haven't seen it: What is scary is that it also works on my mobile, no more holidays for me.... Hans
—
|
10 years ago
|
— | |
|
|
Verilog, combinational logic and modules?
Hi, I'm getting some strange results from the simulator that I don't understand (tried both iverilog and ISim). The design tries to make a combinational assignment inside a module: module gate (input...
4
|
10 years ago
|
4 | |
|
|
3/4 Punctured Convolution encoding
Hi I have to perform punctured convolution encoding at 3/4 rate on Verilog. Ca n anyone provide me the source code to perform puncturing? I am able to per form convolution coding. Don't know how to...
2
|
10 years ago
|
2 |