What do you recommendation for serial communications between FPGA chips? We have one FPGA sending configuration information to multiple other FPGAs. T he FPGAs will be on different boards. The bandwidth is low, although the me ssage transfer needs to be accomplished in well under a microsecond. We hav e a limited number of lines, so an addressable serial scheme is desirable.
Previously we have "rolled our own" asynchronous serial protocol and corres ponding firmware, and transmitted via LVDS. The drawbacks are that a lot of effort went into both developing the firmware, and solving signal integrit y challenges.
I'm wondering what common practices or standard solutions exist? With the g eneric transceivers now available, what out-of-the box techniques are there for using them? Are there cookbook approaches to designing the signal circ uitry? SRIO seems like just the solution, but I really can't tell if it is straightforward to integrate (e.g. the API for the Xilinx Serial RapidIO co re is huge).
Thanks for your thoughts, Charlie