Field-Programmable Gate Arrays

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pipelined algorithm, flow control

Hi, one RTL coding style for pipelined processing goes as follows: - set arguments to function with latency, i.e. memor...
2 comments posted 12yrs
posted by 24789
2 comments posted 12yrs posted by 24789

Parametrized, synthesizable FFT engine

Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length o...
1 comments posted 12yrs
posted by wzab01
1 comments posted 12yrs posted by wzab01

Verilog (Xilinx): Virtual tristate or muxes?

Hi, I've got some FPGA resources that are shared, for example RAM and multiplier. Instead of explicitly muxing the inpu...
7 comments posted 12yrs
posted by 24789
7 comments posted 12yrs posted by 24789

PathFinder Source Code (in C)

Hi Guys, I am currently working on FPGA accelerators for PathFinder algorithm (FPGA routing algorithm). I am planning t...
2 comments posted 12yrs
posted by ziadasic
2 comments posted 12yrs posted by ziadasic

Programming a Digilent S6 Carrier (Spartan 6

Hi, I'm programming the Flash memory in a Digilent "S6 carrier" board. It takes a long time, about 8 minutes. The confi...
4 comments posted 12yrs
posted by 24789
4 comments posted 12yrs posted by 24789

XC9572-15PC84C - need to purchase

Hello All, I am looking to purchase up to 800 pieces of this Xilinx item: XC9572-15PC84C I can also use XC9572-15PC84I...
0 comments posted 12yrs
posted by tiffaniecrocker
0 comments posted 12yrs posted by tiffaniecrocker

XC9572-15PC84C

Hello All, I am looking to purchase up to 800 pieces of this Xilinx item: XC9572-15PC84C I can also use XC9572-15PC84I...
0 comments posted 12yrs
posted by tiffaniecrocker
0 comments posted 12yrs posted by tiffaniecrocker

chip-to-chip serial comms

What do you recommendation for serial communications between FPGA chips? We have one FPGA sending configuration informa...
2 comments posted 12yrs
posted by tickranch
2 comments posted 12yrs posted by tickranch

my first microZed board

Just got this from production: https://dl.dropboxusercontent.com/u/53724080/PCBs/ASP_SN1_top.jpg from previously posted...
21 comments posted 12yrs
posted by jlarkin
21 comments posted 12yrs posted by jlarkin

Math is hard

Hey y'all -- So this is one of those times that my lack of serious math chops is coming round to bite me, and none of m...
25 comments posted 12yrs
posted by rgaddi
25 comments posted 12yrs posted by rgaddi

embedded RAM vs. registers

Hi everyone, I'm trying to optimize the footprint of my firmware on the target device and I realize there are a lot of...
10 comments posted 12yrs
posted by alessandro.basili
10 comments posted 12yrs posted by alessandro.basili

EDA Playground

For those that haven't seen it: http://eda-playground.readthedocs.org/en/latest/ http://www.edaplayground.com/s/example...
0 comments posted 12yrs
posted by hans64
0 comments posted 12yrs posted by hans64

Verilog, combinational logic and modules?

Hi, I'm getting some strange results from the simulator that I don't understand (tried both iverilog and ISim). The des...
4 comments posted 12yrs
posted by 24789
4 comments posted 12yrs posted by 24789

3/4 Punctured Convolution encoding

Hi I have to perform punctured convolution encoding at 3/4 rate on Verilog. Ca n anyone provide me the source code to p...
2 comments posted 12yrs
posted by eyecatcherdear
2 comments posted 12yrs posted by eyecatcherdear