d-flop critical timing

Not that I know of. In the presence of metastability it might not be that well defined as it would probably depend on the clock rate.

Cheers

Phil Hobbs

"Quantization error" perhaps?

I will name it td. The manufacturers practice safe specs by abstaining from naming what happens between setup and hold.

td is the time when the data signal switches.

Is there something you can do with it when you know?

Sylvia.

You could call it "sampling instant" as it is the point (actually a small window) from which regeneration starts bringing the value up to 1 or down to 0. This terminology is used in recent superregenerative literature.

Pere

Or even better, "sampling aperture", in relation to the same parameter on a synchronous ADC.

Indeed, while a comparator is a continuous-time ADC (one bit quantizing), a comparator followed by a D-f/f is a discrete-time, one-bit quantizer.

Or, seeing as a logic input pin is, by definition, an analog to digital converter (just not a very good one, in most cases), we can short-circuit the comparator stage and call a (real) D-f/f a discrete-time ADC.

Though some are pretty reasonable, like LVDS input stages. And for that matter, latching the (digitized) state with a flip-flop, and running, say, a D-S converter, at high speed using spare FPGA pins.

All of which has been talked about, here, before. :-)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com

The data sheets I remember specified a "set-up time" from which the data ha d to be stable vis-a-vis the clock edge and a "hold time" during which the data had to be stable (again vis-a-vis the active clock edge).

In effect a time window anchored to the active clock edge. It lumped togeth er some internal propaganation delays. As someone else has pointed out, for some parts you could get away with a negative set-up time - presumably bec ause the data got to the relevant gate faster than the the clock edge.

If you could tell us which d-type flip-flop we were using, we could dig out the data sheet for you, and identify the relevant page.

--
Bill Sloman, Sydney

Yes. We want to measure the jitter of a logic edge. We can use $100K or so of high-end sampling scope, or maybe we can use one d-flop.

The edge to be measured goes into D, and the "trigger" (what would have been the scope trigger) goes into clock. If we can carefully sweep the trigger through the critical setup/hold boundary, the averaged Q will contain enough information to characterize the jitter of the edge at D.

There seems to be a "dragons lurk here" time between -Tsu and Th which everyone is warned to just avoid. The only papers that I can find, that dare enter this region, are metastability studies, and even they don't fully characterize this flop behavior.

I think we can get below 1 ps RMS equivalent jitter measurement from a fast flop. This will be hard to test.

There is also the possibility of hysteresis, namely that the critical setup/hold boundary time depends on the current state of Q. I think I have seen that before. That effect may have been thermal, since I was working with 10KH single-ended ECL.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

I'd just call it Tsu. If you want to measure the limits where it's not metastable, then use Tsu and Th. They're the measured values, rather than the guaranteed values. If you want to use Tsu(meas) and Th(meas), the thought police will probably find something worse to send you to the re-education camp for.

Ts = sampling time is good. I've never seen it specified.

It would usually be negative (data is sampled before the clock edge) for most flops.

I recall that the default LT Spice d-flop does not make a working shift register, because Ts is 0 or one sim tick or something.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

The width of the region and "location" (wrt, e.g., clock) are dependent on lots of factors -- circuit topology (logic family), process variation, etc. So, putting a hard-and-fast number on a particular "part number" isn't possible without characterizing each device/date code.

And, you're still vulnerable to environmental factors (finite speed of light means conditions IN the device aren't the same ACROSS the device)

I doubt you will find *a* point in time that marks the threshold for Q going HI (in your example) vs. Q staying LO.

Note that *if* the device goes metastable, the time it *stays* in that behavior varies AND its final outcome can also vary. E.g., it can *look* like it's going to toggle to HI but change its mind and end up LO, again.

This will vary with power supply voltage, noise, ambient radiation, etc. as you don't know what will eventually bias an EFFECTIVELY "balanced" condition one way or the other.

Typically (in synchronizer applications), you'd add a second stage AFTER the first DFF and use the clocked out put of that stage to produce your "synchronized signal".

[Note that you needn't clock it with the same signal that clocks the first stage]

But, all this does is improve the odds of NOT seeing a metastable signal at the output of the second (final) stage -- as it relies on characterizing the metastability RECOVERY period of the first DFF (i.e., if you walk out on the tail of the distribution and find a point where it is "very unlikely" that the first stage DFF is

*still* in a metastable state at the time -- dT -- after the first DFF clock edge when you are going to clock the second synchronizer stage) [Obviously, if the output of a single stage synchronizer feeds more than one "load" (in the logic sense), they you end up with a hazard that can lead to unpredictable behavior in the system: "can't happen" actually *does* happen!]

That works for me.

It avoids confusion with the setup time and hold time, has to be somewhere in between those two, and is vaguely reminiscent of a 1-bit ADC.

Since Ts/Th could be interpreted the setup/hold times, any abbreviations would have to be defined explicitly, maybe Ts, Tsu, Tho.

Yeah, I am prepared to believe that.

Different effects will take place at different points/times along the clock rising edge too so it all gets very messy very fast.

piglet

You make an excellent argument that oscilloscopes can't work. Actually, that nothing can work.

We would find the delta-T where the probability of Q-high is 50%. We can average lots of shots. And we can wait out, or just average in, any metastability effects. If a fast ECL flop does go metastable, it will resolve in nanoseconds; we won't even know when that happens.

Again, we will average the value of Q over many shots.

How can electronics ever work, with all that stuff going on?

I expect that the big fat metastable shots happen at the ideal delta-t that we want to find.

I don't want synchronizer predictability, I want to find the setup time where Q is exactly unpredictable, randomly high 50% of the time. And then characterize the statistical behavior of Q as a function of small time deltas. What's wrong with doing that? (Other than it's hard to do.)

I suppose this sort of thing has been researched - it's pretty obvious

- but some googling didn't find anything. If anything, most data sheets and papers seem to avoid the issue.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

It IS a 1-bit ADC!

The common convention is Tsu and Th, so "Ts" is available. Use Tsamp maybe to be clear.

One of my guys was measuring an ECL flop on Friday (while I was meeting with some customers and he was having all the fun) so I may have some real data on Monday. I'm betting the critical window will be under 1 ps wide.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

It fails because the delay is zero, so the D on one flop changes before the Q on the next flop gets "sampled"

Flop data sheets already use Tsu and Th. These are the "safe operating boundaries" but only vaguely suggest what the sampling time might be... somewhere inbetween, maybe roughly midway. I like "Tsamp".

It should only have one value, not two. It is a statistical measurement.

I suspect it will be pretty consistant for a given part, especially for an all-differential ECL flop where the timings, diff zero crossings, are clearly defined.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

The metastable state is usually manifested by the output being neither high nor low for an indeterminate time. It sits "halfway" until it "decides which way to go".

An alternative manifestation is that the output oscillates for an indeterminate time.

In either case, I'm not sure that "randomly high 50% of the time" has much meaning.

A /few/ scope traces can be found by googling for "synchronizer metastable state image", but personally I'd prefer to look in the old IEEE or IEE literature; IIRC they usually came with pictures.

is someone's personal bibliography.

The technique you describe is a recurring theme in the Time-Nuts forum. It is used in several precison timing applications, such as zero cross detection in DMTD applications, and is used in the White Rabbit timing synchronizattion in CERN. Here are a few links:

snipped-for-privacy@febo.com/msg16711.html diode-mixer

b.pdf

Trivial to test. Just feed the same edge to D and Clock. Use a small time delay to center the transition on the decision threshold. Adjust delay to sweep through the threshold. Integrate the output. The histogram shows the peak and the slope. Find 1st sigma point. That is your d-flop measurement jitter.

Extend this to include the trigger circuit jitter. This gives your sysem jitter. Now you are ready to measure jitter on input signals. You can probably use the difference of squares to separate the input jitter.

Some of the above papers discuss measurements down to 26 fs.

Thermal drift is a problem. It has been mentioned in several NIST papers.