29 discussions on ElectronDepot about the Xilinx PPC405: what owners asked, what went wrong, and what fixed it.
Many engineers today have Linux on Desktop as main-OS. Many engineerstoday use Open Source products because of their quality, stability,and configurability.Today I see no alternative to use Xilinx or Alteras Web Packs. Bothare in a very sad...
I am probably opening a can of worms, but why are FPGAs so slow?The CPU cores at represent an ever growing number of excellent and very practical, but slow processor implementations. What I mean is 240-500Mhz FPGAs, when market CPUs are in...
Hello to the group!I've been struggling to get the Xilinx IOCM and DOCM modules workingwith the PPC405 in my current design and I'm starting to run out ofideas. The first iteration of the design uses cached SDRAM via the PLBto store/load...
Hi folks,I wonder how do you fight (bypass) problems with a PPC405 (XilinxVirtex-4FX) caching problems - silicon errata available atftp://I tried disabling cache, but performance drops significantly.I also find this code snippet in GSRD2...
Hello,I am looking for some help with a particularily nasty problem I haverun into,Out of our 10 prototype Virtex-4-FX20 (CES2 stepping) boards, roughlyhalf are exhibiting an issue with the PPC405 starting up out of reset.After powerup, the...
ML403 - Virtex4 - PPC405 - Xilinx EDK V10.1Hi,I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). I have used the wizard to configure basically the same design, but with the FPU included - this is...