20.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Programmable Cyclic Redundancy Check (CRC)" (DS39714).
The programmable CRC generator offers the following features:
- User-programmable polynomial CRC equation
- Interrupt output
- Data FIFO
The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the X<15:1> bits (CRCXOR<15:1>) and the PLEN<3:0> bits (CRCCON<3:0>), respectively.
Consider the following equation:
EQUATION 20-1: CRC POLYNOMIAL
$$x^{16} + x^{12} + x^5 + 1$$
To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 20-1.
TABLE 20-1: EXAMPLE CRC SETUP \begin{tabular}{|l|l|} \hline \textbf{Bit Name} & \textbf{Bit Value} \ \hline PLEN<3:0> & 1111 \ \hline X<15:1> & 000100000010000 \ \hline \end{tabular}
Note that for the value of X<15:1>, the 12th bit and the 5th bit are set to '1', as required by the equation. The 0 bit, required by the equation, is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X<15:1> bits do not have the 0 bit or the 16th bit.
A simplified block diagram of the module is shown in Figure 20-1. The general topology of the shift engine is shown in Figure 20-2.
FIGURE 20-1: CRC BLOCK DIAGRAM
FIGURE 20-2: CRC SHIFT ENGINE DETAIL
Note 1: Each XOR stage of the shift engine is programmable. See text for details. 2: Polynomial Length n is determined by ([PLEN<3:0>] + 1).
20.1 User Interface
20.1.1 DATA INTERFACE
To start serial shifting, a '1' must be written to the CRCGO bit.
The module incorporates a FIFO that is 8 deep when PLEN<3:0> (CRCCON<3:0>) > 7 and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN<3:0> = 5, then the size of the data is PLEN<3:0> + 1 = 6. When loading data, the two MSbs of the data byte are ignored.
Once data is written into the CRCWDAT MSb (as defined by PLENx), the value of VWORD<4:0> (CRCCON<12:8>) increments by one. When CRCGO = 1 and VWORDx > 0, a word of data to be shifted is moved from the FIFO into the shift engine. When the data word moves from the FIFO to the shift engine, the VWORDx bits decrement by one. The serial shifter continues to receive data from the FIFO, shifting until the VWORDx bits reach 0. The last bit of data will be shifted through the CRC module (PLENx + 1)/2 clock cycles after the VWORDx bits reach 0. This is when the module is completed with the CRC calculation.
Therefore, for a given value of PLENx, it will take (PLENx + 1)/2 * VWORDx number of clock cycles to complete the CRC calculations.
When the VWORD<4:0> bits reach 8 (or 16), the CRCFUL bit will be set. When the VWORD<4:0> bits reach 0, the CRCMPT bit will be set.
To continually feed data into the CRC engine, the recommended mode of operation is to initially "prime" the FIFO with a sufficient number of words, so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to '1'. From that point onward, the VWORDx bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO.
To empty words already written into a FIFO, the CRCGO bit must be set to '1' and the CRC shifter allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the VWORDx Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 20.1.2 "Interrupt Operation").
At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORDx bits is done.
20.1.2 INTERRUPT OPERATION
When the VWORD<4:0> bits make a transition from a value of '1' to '0', an interrupt will be generated. Note that the CRC calculation is not complete at this point; an additional time of (PLEN + 1)/2 clock cycles is required before the output can be read.
20.2 Operation in Power Save Modes
20.2.1 SLEEP MODE
If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes.
20.2.2 IDLE MODE
To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.
20.3 Registers
There are four registers used to control programmable CRC operation:
- CRCCON
- CRCXOR
- CRCDAT
- CRCWDAT
REGISTER 20-1: CRCCON: CRC CONTROL REGISTER
Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7 or 16 when PLEN<3:0> ≤ 7. bit 7 CRCFUL: CRC FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: CRC Start bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.
REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| X15 | X14 | X13 | X12 | X11 | X10 | X9 | X8 |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | U-0 |
|---|---|---|---|---|---|---|---|
| X7 | X6 | X5 | X4 | X3 | X2 | X1 | — |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-1 X<15:1>: XOR of Polynomial Term Xⁿ Enable bits
bit 0 Unimplemented: Read as ‘0’
21.0 10-BIT HIGH-SPEED A/D CONVERTER
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “10-Bit A/D Converter” (DS39705).
The 10-bit A/D Converter has the following key features:
- Successive Approximation (SAR) conversion
- Conversion speeds of up to 500 ksps
- Up to 13 analog input pins
- External voltage reference input pins
- Automatic Channel Scan mode
- Selectable conversion trigger source
- 16-word conversion result buffer
- Selectable Buffer Fill modes
- Four result alignment options
- Operation during CPU Sleep and Idle modes
Depending on the particular device pinout, the 10-bit A/D Converter can have up to three analog input pins, designated AN0 through AN12. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and the external voltage reference input configuration will depend on the specific device.
A block diagram of the A/D Converter is shown in Figure 21-1.
To perform an A/D conversion:
-
Configure the A/D module: a) Select the port pins as analog inputs (AD1PCFG<15:0>). b) Select the voltage reference source to match the expected range on the analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>). e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). f) Select the interrupt rate (AD1CON2<5:2>). g) Turn on the A/D module (AD1CON1<15>).
-
Configure the A/D interrupt (if required): a) Clear the AD1IF bit. b) Select the A/D interrupt priority.
FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Note 1: Analog Channels, AN6 through AN8, are available on 44-pin devices only. 2: Band Gap Voltage (V_BG) reference is internally connected to Analog Channel AN15, which does not appear on any pin.
DS39881E-page 194 © 2010-2013 Microchip Technology Inc.
REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1
| R/W-0 | U-0 | R/C-0 | U-0 | U-0 | U-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| ADON⁽¹⁾ | — | ADSIDL | — | — | — | FORM1 | FORM0 |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | U-0 | U-0 | R/W-0 | R/W-0, HSC | R/W-0, HSC |
|---|---|---|---|---|---|---|---|
| SSRC2 | SSRC1 | SSRC0 | — | — | ASAM | SAMP | DONE |
| bit 7 | bit 0 |
Legend:
- R = Readable bit
- W = Writable bit
- C = Clearable bit
- U = Unimplemented bit, read as ‘0’
- HSC = Hardware Settable/Clearable bit
- -n = Value at POR
- ‘1’ = Bit is set
- ‘0’ = Bit is cleared
- x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit⁽¹⁾
1 = A/D Converter module is operating
0 = A/D Converter is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: A/D Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5
SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
10x = Reserved
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
bit 4-3
Unimplemented: Read as ‘0’
bit 2
ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1
SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold (S/H) amplifier is sampling input
0 = A/D Sample-and-Hold amplifier is holding
bit 0
DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is NOT done
Note 1: The ADC1BUFn registers do not retain their values when ADON is cleared. Read out any conversion values from the buffer before disabling the module.
REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2
| R/W-0 | R/W-0 | R/W-0 | U-0 | U-0 | R/W-0 | U-0 | U-0 |
|---|---|---|---|---|---|---|---|
| VCFG2 | VCFG1 | VCFG0 | — | — | CSCNA | — | — |
| bit 15 | bit 8 |
| R-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| BUFS | — | SMPI3 | SMPI2 | SMPI1 | SMPI0 | BUFM | ALTS |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
| VCFG<2:0> | VR+ | VR- |
|---|---|---|
| 000 | AVDD* | AVSS* |
| 001 | External VREF+ Pin | AVSS* |
| 010 | AVDD* | External VREF- Pin |
| 011 | External VREF+ Pin | External VREF- Pin |
| 1xx | AVDD* | AVSS* |
- AVDD and AVSS inputs are tied to VDD and Vss on 28-pin devices.
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling Buffer 08-0F, user should access data in 00-07
0 = A/D is currently filling Buffer 00-07, user should access data in 08-0F
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
...
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)
0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples
0 = Always uses MUX A input multiplexer settings
REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3
| R/W-0 | U-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| ADRC | — | — | SAMC4 | SAMC3 | SAMC2 | SAMC1 | SAMC0 |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| ADCS7 | ADCS6 | ADCS5 | ADCS4 | ADCS3 | ADCS2 | ADCS1 | ADCS0 |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADRC: A/D Conversion Clock Source bit
1 = A/D internal RC clock
0 = Clock derived from system clock
bit 14-13
Unimplemented: Read as ‘0’
bit 12-8
SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
……
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0
ADCS<7:0>: A/D Conversion Clock Select bits
11111111
…… = Reserved
01000000
00111111 = 64 • Tcy
……
00000001 = 2 • Tcy
00000000 = Tcy
REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER
| R/W-0 | U-0 | U-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| CH0NB | — | — | — | CH0SB3(1,2) | CH0SB2(1,2) | CH0SB1(1,2) | CH0SB0(1,2) |
| bit 15 | bit 8 |
| R/W-0 | U-0 | U-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| CH0NA | — | — | — | CH0SA3(1,2) | CH0SA2(1,2) | CH0SA1(1,2) | CH0SA0(1,2) |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 14-12
Unimplemented: Read as ‘0’
bit 11-8
CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
. . . .
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 6-4
Unimplemented: Read as ‘0’
bit 3-0
CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits(1,2)
1111 = Channel 0 positive input is AN15 (band gap voltage reference)
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
. . . .
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
Note 1: Combinations, ‘1101’ and ‘1110’, are unimplemented; do not use.
2: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; do not use.
REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
| R/W-0 | U-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| PCFG15 | — | — | PCFG12 | PCFG11 | PCFG10 | PCFG9 | PCFG8(1) |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| PCFG7(1) | PCFG6(1) | PCFG5 | PCFG4 | PCFG3 | PCFG2 | PCFG1 | PCFG0 |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PCFG15: Analog Input Pin Configuration Control bit
1 = Band gap voltage reference is disabled
0 = Band gap voltage reference is enabled
bit 14-13
Unimplemented: Read as ‘0’
bit 12-0
PCFG<12:0>: Analog Input Pin Configuration Control bits(1)
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
Note 1: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; leave these corresponding bits set.
REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER
| R/W-0 | U-0 | U-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| CSSL15 | — | — | CSSL12 | CSSL11 | CSSL10 | CSSL9 | CSSL8(1) |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| CSSL7(1) | CSSL6(1) | CSSL5 | CSSL4 | CSSL3 | CSSL2 | CSSL1 | CSSL0 |
| bit 7 | bit 0 |
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CSSL15: Band Gap Reference Input Pin Scan Selection bit
1 = Band gap voltage reference channel is selected for input scan
0 = Band gap voltage reference channel is omitted from input scan
bit 14-13
Unimplemented: Read as ‘0’
bit 12-0
CSSL<12:0>: A/D Input Pin Scan Selection bits(1)
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
Note 1: Analog Channels, AN6, AN7 and AN8, are unavailable on 28-pin devices; leave these corresponding bits cleared.
EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)
$T_AD = T_CY \cdot (ADCS + 1)$
$ADCS = \fracT_ADT_CY - 1$
Note 1: Based on $T_{CY}$ = 2 * $T_{OSC}$; Doze mode and PLL are disabled.
FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
Legend: $C_{PIN}$ = Input Capacitance $V_T$ = Threshold Voltage $I_{LEAKAGE}$ = Leakage Current at the pin due to various junctions $R_{IC}$ = Interconnect Resistance $R_{SS}$ = Sampling Switch Resistance $C_{HOLD}$ = Sample/Hold Capacitance (from DAC)
Note: $C_{PIN}$ value depends on device package and is not tested. The effect of $C_{PIN}$ is negligible if R_S \leq 5 k\Omega.
FIGURE 21-3: A/D TRANSFER FUNCTION
NOTES:
DS39881E-page 202 © 2010-2013 Microchip Technology Inc.
22.0 COMPARATOR MODULE
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Output Compare” (DS39706).
FIGURE 22-1: COMPARATOR I/O OPERATING MODES
Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information.
REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER
| R/W-0 | U-0 | R/C-0 | R/C-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| CMIDL | — | C2EVT | C1EVT | C2EN | C1EN | C2OUTEN⁽¹⁾ | C1OUTEN⁽²⁾ |
| bit 15 | bit 8 |
| R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
|---|---|---|---|---|---|---|---|
| C2OUT | C1OUT | C2INV | C1INV | C2NEG | C2POS | C1NEG | C1POS |
| bit 7 | bit 0 |
Legend:
- R = Readable bit
- W = Writable bit
- U = Unimplemented bit, read as ‘0’
- -n = Value at POR
- ‘1’ = Bit is set
- ‘0’ = Bit is cleared
- x = Bit is unknown
- C = Clearable bit
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1 = When device enters Idle mode, module does not generate interrupts; module is still enabled
0 = Continues normal module operation in Idle mode
bit 14
Unimplemented: Read as ‘0’
bit 13
C2EVT: Comparator 2 Event
1 = Comparator output changed states
0 = Comparator output did not change states
bit 12
C1EVT: Comparator 1 Event
1 = Comparator output changed states
0 = Comparator output did not change states
bit 11
C2EN: Comparator 2 Enable
1 = Comparator is enabled
0 = Comparator is disabled
bit 10
C1EN: Comparator 1 Enable
1 = Comparator is enabled
0 = Comparator is disabled
bit 9
C2OUTEN: Comparator 2 Output Enable⁽¹⁾
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 8
C1OUTEN: Comparator 1 Output Enable⁽²⁾
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
0 = C2 VIN+ > C2 VIN-
1 = C2 VIN+ < C2 VIN-
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
0 = C1 VIN+ > C1 VIN-
1 = C1 VIN+ < C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output is inverted
0 = C2 output is not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output is inverted
0 = C1 output is not inverted
bit 3
C2NEG: Comparator 2 Negative Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to VIN-
See Figure 22-1 for the Comparator modes.
bit 2
C2POS: Comparator 2 Positive Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to CVREF
See Figure 22-1 for the Comparator modes.
bit 1
C1NEG: Comparator 1 Negative Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to VIN-
See Figure 22-1 for the Comparator modes.
bit 0
C1POS: Comparator 1 Positive Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to CVREF
See Figure 22-1 for the Comparator modes.
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
NOTES:
DS39881E-page 206 © 2010-2013 Microchip Technology Inc.