Microchip PIC24 datasheet

28/44-Pin General Purpose, 16-Bit Flash Microcontrollers

High-Performance CPU

• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture:
  • 76 base instructions
  • Flexible addressing modes
• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory

Special Microcontroller Features

• Operating Voltage Range of 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
  • 10,000 erase/write
  • 20-year data retention minimum
• Power Management modes:
  • Sleep, Idle, Doze and Alternate Clock modes
  • Operating current: 650 μA/MIPS, typical at 2.0V
  • Sleep current: 150 nA, typical at 2.0V
• Fail-Safe Clock Monitor (FSCM) Operation:
  • Detects clock failure and switches to on-chip, low-power RC oscillator
• On-Chip, 2.5V Regulator with Tracking mode
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins
• JTAG Boundary Scan Support

Analog Features

• 10-Bit, up to 13-Channel Analog-to-Digital Converter:
  • 500 ksps conversion rate
  • Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable Input/Output Configuration

Peripheral Features

• Peripheral Pin Select (PPS):
  • Allows independent I/O mapping of many peripherals
  • Up to 26 available pins (44-pin devices)
  • Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes
• 8-Bit Parallel Master/Slave Port (PMP/PSP):
  • Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices
  • Programmable polarity on control lines
• Hardware Real-Time Clock/Calendar (RTCC):
  • Provides clock, calendar and alarm functions
• Programmable Cyclic Redundancy Check (CRC)
• Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer
• Two I²C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing
• Two UART modules:
  • Supports RS-485, RS-232, and LIN/J2602
  • On-chip hardware encoder/decoder for IrDA®
  • Auto-wake-up on Start bit
  • Auto-Baud Detect
  • 4-level deep FIFO buffer
• Five 16-Bit Timers/Counters with Programmable Prescaler
• Five 16-Bit Capture Inputs
• Five 16-Bit Compare/PWM Outputs
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to 3 External Interrupt Sources

Pin Diagrams

28-Pin SPDIP, SSOP, SOIC

28-Pin QFN(1)

Legend: RPN represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.

Note 1: Back pad on QFN devices should be connected to Vss.

Pin Diagrams (Continued)

44-Pin QFN(1)

Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Note 1: Back pad on QFN devices should be connected to Vss.

Pin Diagrams (Continued)

44-Pin TQFP

Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.

DS39881E-page 4 © 2010-2013 Microchip Technology Inc.

Table of Contents

• 1.0 Device Overview ........ 7
• 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........ 17
• 3.0 CPU ........ 23
• 4.0 Memory Organization ........ 29
• 5.0 Flash Program Memory ........ 47
• 6.0 Resets ........ 53
• 7.0 Interrupt Controller ........ 59
• 8.0 Oscillator Configuration ........ 95
• 9.0 Power-Saving Features ........ 103
• 10.0 I/O Ports ........ 105
• 11.0 Timer1 ........ 125
• 12.0 Timer2/3 and Timer4/5 ........ 127
• 13.0 Input Capture ........ 133
• 14.0 Output Compare ........ 135
• 15.0 Serial Peripheral Interface (SPI) ........ 141
• 16.0 Inter-Integrated Circuit (I²C™) ........ 151
• 17.0 Universal Asynchronous Receiver Transmitter (UART) ........ 159
• 18.0 Parallel Master Port (PMP) ........ 167
• 19.0 Real-Time Clock and Calendar (RTCC) ........ 177
• 20.0 Programmable Cyclic Redundancy Check (CRC) Generator ........ 189
• 21.0 10-Bit High-Speed A/D Converter ........ 193
• 22.0 Comparator Module ........ 203
• 23.0 Comparator Voltage Reference ........ 207
• 24.0 Special Features ........ 209
• 25.0 Development Support ........ 219
• 26.0 Instruction Set Summary ........ 223
• 27.0 Electrical Characteristics ........ 231
• 28.0 Packaging Information ........ 251
• Appendix A: Revision History ........ 267
• Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ........ 268
• Index ........ 269
• The Microchip Web Site ........ 273
• Customer Change Notification Service ........ 273
• Customer Support ........ 273
• Reader Response ........ 274
• Product Identification System ........ 275

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DS39881E-page 6 © 2010-2013 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

This document contains device-specific information for the following devices:

• PIC24FJ16GA002
• PIC24FJ32GA002
• PIC24FJ48GA002
• PIC24FJ64GA002
• PIC24FJ16GA004
• PIC24FJ32GA004
• PIC24FJ48GA004
• PIC24FJ64GA004

This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ64GA004 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don’t require the numerical processing power of a digital signal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces
• Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data)
• A 16-element working register array with built-in software stack support
• A 17 x 17 hardware multiplier with support for integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’
• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FJ64GA004 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:

• On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.
• Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat.
• Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.

1.1.3 OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC24FJ64GA004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include:

• Two Crystal modes using crystals or ceramic resonators.
• Two External Clock modes offering the option of a divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier, available to the External Oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz.
• A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.

The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve.

The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 28-pin to 44-pin devices.

The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.

1.2 Other Special Features

• Communications: The PIC24FJ64GA004 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I²C modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select (PPS) feature, two independent UARTs with built-in IrDA encoder/decoders and two SPI modules.
• Peripheral Pin Select (PPS): The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins.
• Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes.
• Real-Time Clock/Calendar (RTCC): This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.
• 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.

1.3 Details on Individual Family Members

Devices in the PIC24FJ64GA004 family are available in 28-pin and 44-pin packages. The general block diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in two ways:

1. Flash program memory (64 Kbytes for PIC24FJ64GA devices, 48 Kbytes for PIC24FJ48GA devices, 32 Kbytes for PIC24FJ32GA devices and 16 Kbytes for PIC24FJ16GA devices).
2. Internal SRAM memory (4k for PIC24FJ16GA devices, 8k for all other devices in the family).
3. Available I/O pins and ports (21 pins on 2 ports for 28-pin devices and 35 pins on 3 ports for 44-pin devices).

All other features for devices in this family are identical. These are summarized in Table 1-1.

A list of the pin features that are available on the PIC24FJ64GA004 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY

Note 1: Peripherals are accessible through remappable pins.

FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. 2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled. 3: Peripheral I/Os are accessible through remappable pins.

DS39881E-page 10 © 2010-2013 Microchip Technology Inc.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS

Legend: TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I²C™ = I²C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

DS39881E-page 12 © 2010-2013 Microchip Technology Inc.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I²C™ = I²C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Legend: TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I²C™ = I²C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.