Field-Programmable Gate Arrays

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How to simulate baud rate generator?

I've gotten the following code for the baudrate generator from opencores I've created a Test Bench Waveform for it from...
6 comments posted 18yrs
posted by me75
6 comments posted 18yrs posted by me75

ps2 mouse initialization fails

Hi, I tried out 2 mouse modules. Both get stuck in the mouse initialization process. The mouse does not respond. The mo...
4 comments posted 18yrs
posted by me
4 comments posted 18yrs posted by me

VHDL code for DDFS

hello, i want a simple VHDL code for DDFS. its really very urgent. anyon who is having that VHDL code plz plz send me as...
7 comments posted 18yrs
posted by roji.sweet
7 comments posted 18yrs posted by roji.sweet

multicyle and false path in FPGA Design

Hi All, How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthes...
3 comments posted 18yrs
posted by ekavirsrikanth
3 comments posted 18yrs posted by ekavirsrikanth

Help with Microblaze timer peripheral

Hi everyone, I am a begginer with microblaze, and I am trying to do some practice code in a Spartan3 Development Boards...
0 comments posted 18yrs
posted by Alfredo.Taddei
0 comments posted 18yrs posted by Alfredo.Taddei

Chipscope data port limitation to 256 bits

Hi I have a bit a problem, I would like to capture the status of 16 registers in my architecture each of them 32 bits l...
4 comments posted 18yrs
posted by Clemens
4 comments posted 18yrs posted by Clemens

Dynamic partial reconfiguration on virtex devices

Hi all, I'm working on dynamic partial reconfiguration on a virtex 4 (sx35) fpga. I would to use hwicap to make interna...
0 comments posted 18yrs
posted by paolo.furia
0 comments posted 18yrs posted by paolo.furia

Call for participation in VLSI 2009 in New Delhi.

Friends, As you all know, the 22nd conference on VLSI Design would be held in New Delhi from January 5 to 9th 2009 at T...
0 comments posted 18yrs
posted by vlsiconference
0 comments posted 18yrs posted by vlsiconference

oversampling serializer?

Hi everyone, I'm supposed to implement a serializer where the parallel data and clock arrive from outside the chip and...
4 comments posted 18yrs
posted by kal
4 comments posted 18yrs posted by kal

logical net 'NET' has no load

Ive seen posts on this error in VHDL a few times around here, but I am still unsure how to get rid of this error so my...
5 comments posted 18yrs
posted by metalimi
5 comments posted 18yrs posted by metalimi

Regarding Xilinx tool

My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can...
2 comments posted 18yrs
posted by pvprabhuraj
2 comments posted 18yrs posted by pvprabhuraj

Configure registers of CMOS Sensor by Spartan3

Hi, I am trying to configure the registers on the MT9T001 Image sensor using a Spartan3 board. I fed a 50MHz to the SCL...
2 comments posted 18yrs
posted by Kicn2008
2 comments posted 18yrs posted by Kicn2008