Latest threads in Field-Programmable Gate Arrays

VHDL code for DDFS

hello, i want a simple VHDL code for DDFS. its really very urgent. anyon who is having that VHDL code plz plz send me as...

7 18yrs

roji.sweet

7 18yrs roji.sweet

multicyle and false path in FPGA Design

Hi All, How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthes...

3 18yrs

ekavirsrikanth

3 18yrs ekavirsrikanth

Help with Microblaze timer peripheral

Hi everyone, I am a begginer with microblaze, and I am trying to do some practice code in a Spartan3 Development Boards...

0 18yrs

Alfredo.Taddei

0 18yrs Alfredo.Taddei

Chipscope data port limitation to 256 bits

Hi I have a bit a problem, I would like to capture the status of 16 registers in my architecture each of them 32 bits l...

4 18yrs

Clemens

4 18yrs Clemens

Low cost solution to program Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK

Yes, how many times I don't write here, maybe about 6 years, from my thesis on a qpsk modulator on a Virtex 1000, I don...

5 18yrs

postmaster

5 18yrs postmaster

Dynamic partial reconfiguration on virtex devices

Hi all, I'm working on dynamic partial reconfiguration on a virtex 4 (sx35) fpga. I would to use hwicap to make interna...

0 18yrs

paolo.furia

0 18yrs paolo.furia

Call for participation in VLSI 2009 in New Delhi.

Friends, As you all know, the 22nd conference on VLSI Design would be held in New Delhi from January 5 to 9th 2009 at T...

0 18yrs

vlsiconference

0 18yrs vlsiconference

oversampling serializer?

Hi everyone, I'm supposed to implement a serializer where the parallel data and clock arrive from outside the chip and...

4 18yrs

kal

4 18yrs kal

Question: What are the tricks mentioned on Viterbi Decoder Wikipedia page?

On this wiki page on Viterbi Decoder : http://en.wikipedia.org/wiki/Viterbi_decoder In the TBU section, it reads "Note...

0 18yrs

jack.harvard

0 18yrs jack.harvard

logical net 'NET' has no load

Ive seen posts on this error in VHDL a few times around here, but I am still unsure how to get rid of this error so my...

5 18yrs

metalimi

5 18yrs metalimi

Xilinx ISE impact outputs bad idcode when in batch mode but works in gui mode

Hi, I am trying to create a batch file to load a bit file into an FPGA (Spartan 3E 500 -5 PQ208). I used the following...

1 18yrs

axr0284

1 18yrs axr0284

Regarding Xilinx tool

My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can...

2 18yrs

pvprabhuraj

2 18yrs pvprabhuraj

Configure registers of CMOS Sensor by Spartan3

Hi, I am trying to configure the registers on the MT9T001 Image sensor using a Spartan3 board. I fed a 50MHz to the SCL...

2 18yrs

Kicn2008

2 18yrs Kicn2008

Can I store the output of my FPGA logic inside FPGA memory for debug data values?

Hi, I am using altera FPGA. How can I put the output of my logic into the FPGA internal memories(assuming I have unused...

6 18yrs

bajajk

6 18yrs bajajk

Help Needed - LPC Bus Interface

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming fro...

0 18yrs

me75

0 18yrs me75