Field-Programmable Gate Arrays

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protocol layer

please tell me if any one know or have core of PL (protocol layer) in usb core. please tell me if any one know about PL...
1 comments posted 18yrs
posted by hmmudassir82
1 comments posted 18yrs posted by hmmudassir82

full timing diagram

Please tell any link from i would easily download full timing diagram of all internal block diagrams of usb core. Pleas...
0 comments posted 18yrs
posted by hmmudassir82
0 comments posted 18yrs posted by hmmudassir82

free of bugs

Please tell me any link from i would easily download usb core which will be free of bugs.
5 comments posted 18yrs
posted by hmmudassir82
5 comments posted 18yrs posted by hmmudassir82

Read files from Compact Flash

Hi all, I'm working on a dynamically reconfigurable project on ML402 (virtex-4 sx35) and, for this, I have to load part...
0 comments posted 18yrs
posted by paolo.furia
0 comments posted 18yrs posted by paolo.furia

XAPP240 - Design Files

Hi newsgroup, does someone know whether there are design files available for Xilinx application note "XAPP240 - High-Sp...
3 comments posted 18yrs
posted by ALuPin
3 comments posted 18yrs posted by ALuPin

usb core block diagram

I am mudassir. I want to get internal block diagram of usb core 2.0 or any other. Please give me if any one have this i...
1 comments posted 18yrs
posted by hmmudassir82
1 comments posted 18yrs posted by hmmudassir82

defunct Platform USB cable

Yesterday, one of my Platform USB cables ceased working. I opened the box and found cold solder joints at the USB conne...
0 comments posted 18yrs
posted by dk4xp
0 comments posted 18yrs posted by dk4xp

FPL 2008 : Call for Participation

FPL International Conference on Field Programmable Logic and Applications Call for Participation The early registration...
0 comments posted 18yrs
posted by m8pple
0 comments posted 18yrs posted by m8pple

Xilinx Spartan-3E Microblaze Program Execution

Hello all, I am a beginner with the Xilinx EDK and Platform Studio software for programming a Microblaze processor. I h...
0 comments posted 18yrs
posted by ray.delvecchio
0 comments posted 18yrs posted by ray.delvecchio

Xilinx/Altera gate equivalence

Are there any rules of thumb to figure out the equivalent number of logic resources needed to implement the same design...
12 comments posted 18yrs
posted by dudesinmexico
12 comments posted 18yrs posted by dudesinmexico

AURORA streaming

Target FPGA: Virtex II PRO I generated 2 designs including 4 AURORA single lane CORE each, configured in streaming : Th...
0 comments posted 18yrs
posted by erwandav
0 comments posted 18yrs posted by erwandav

No open-drain in V5 to drive an external LED?

HI, on our PCB there is a LED directly connected to a Virtex5 I/O pad. The LED is connected through a series resistor t...
3 comments posted 18yrs
posted by heinerlitz
3 comments posted 18yrs posted by heinerlitz

unified protocol

Hai, Any anyone can list test cases to verify unified protocol. regards, raj
9 comments posted 18yrs
posted by rajesh.obli
9 comments posted 18yrs posted by rajesh.obli

Xilinx Virtex 4

I need help with immediate delivery of two Virtex 4 FPGA's. The part numbers are XC4VLX80-11FFG1148C (50pcs) and XC4VLX...
1 comments posted 18yrs
posted by jon
1 comments posted 18yrs posted by jon

Fifo Simulation Error

I've initiated the component and the instance according to the .vho files created along when I created my FIFO with the...
11 comments posted 18yrs
posted by me75
11 comments posted 18yrs posted by me75