Hello everyone
I want to do a for loop in order to repeat the same construction and use the number of the loop to create the index to take the desirated part of the bus , the problem is that i don't know how to do it and i don't know what to look for in google , i would like to do this enable_reg(2*i+1 downto 2*i)
my code:
for i in 0 to 11 loop case enable_reg(2*i+1 downto 2*i) is when "00" =>
enable_output(i) enable_output(i) enable_output(i)
In VHDL it is "end loop" rather than "end for". Apart from that, it's difficult to work out what you are trying to achieve - and your level of expertise - from so little information...
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It appears you are taking a 24-bit bus and splitting up into pairs to derive 12 individual output enable signals, each which can go 0, 1, or a single enable called disc_enable(0). I'm not sure why you are using
24-bit bus to gate the passing of a single driving enable signal--it seems like an additional of complexity perhaps not necessary but I could be wrong--but a generate statement would work. Google "VHDL generate."
I found out how to do what I want by using variable in which I compute my index and then use this computed variable for my index in the vector extraction so it gives something like that
index_i :=3D 2*i; index_j :=3D 2*i+1; temp :=3D enable_reg(index_j downto index_i);
and what that does: In my systeme i have 3 discrete inputs for enable of outputs I have 12 outputs and 1 register of 24bits wich defines which configure the enable to use for the outputs, like this each output has 2 bit to define the output enable that is active on the ouput. enable reg is a register
and for rc
I think VHDL is the same for dummies and expert just one would know better and go faster
anyway thanks for looking at my problem even i fixed by myself (maybe should i 've asked it in vhdl group not fpga)
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