Hi,
I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need to use the Quartus Lite Edition. One of essential things in the design is the usage of "scoped timing constraints" (obtained in Vivado with SCOPED_TO_REF attribute). I have found that a similar option is available in Quartus as "entity-bound SDC files". My question is if that option is available in the Lite version? If not, is it possible to emulate the "SCOPED_TO_REF" functionality otherwise in the Lite version?
TIA & Best regards, Wojtek