ADCs in FPGAs

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I have looked at ADCs in FPGAs but never built one.  Obviously sigma delta  
is a good way to go as it can be done all digitally, or almost so.  I'm not
 completely clear on how to do it.  

Lattice has a reference design using an LVDS receiver as a comparator.  The
y use an RC filter on the output bit as the reference voltage for the input
.  I'm having trouble relating this to the typical block diagram of the sig
ma delta converter.  Is this circuit the same thing?  

Anyone built one of these?  Is it practical to expect 12 bits of resolution
 with a 16 MHz clock rate and 1 kHz sample rate?  By 12 bits I mean a solid
 12 bits of accuracy... the word width can be wider if that helps any.  

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  Rick C.

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Re: ADCs in FPGAs
On 31/08/2020 02:57, Rick C wrote:
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I would not be confident at getting 12 bits accuracy inside a fast
digital part - it's very difficult to have your supplies and references
stable enough, and to avoid switching noise from the digital parts
interfering with the analogue.  A 1 kHz sample rate 14-bit ADC chip with


Re: ADCs in FPGAs
On 31/08/2020 01:57, Rick C wrote:
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I've never tried - getting a decent ADC into a functioning FPGA seems  
like a very difficult task.
Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4  
will do you, it has programmable gain, multiplexer, choice of up to 8  
channels, 15 ENOB etc.

MK


Re: ADCs in FPGAs
On Monday, August 31, 2020 at 4:32:56 AM UTC-4, Michael Kellett wrote:
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lta is a good way to go as it can be done all digitally, or almost so.  I'm
 not completely clear on how to do it.
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 They use an RC filter on the output bit as the reference voltage for the i
nput.  I'm having trouble relating this to the typical block diagram of the
 sigma delta converter.  Is this circuit the same thing?
Quoted text here. Click to load it
tion with a 16 MHz clock rate and 1 kHz sample rate?  By 12 bits I mean a s
olid 12 bits of accuracy... the word width can be wider if that helps any.
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Yes, I looked at that part.  It's not as available as our target which is 1
0,000 stocked... yes, that may sound unrealistic, but many devices meet tha
t requirement even if the FPGAs typically don't.  Also it is a bit complica
ted to use.  Configuring it from an FPGA is a bother... configuring it from
 anything is a bother.  lol  But it certainly is an option.  Very likely I  
will include both options, internal ADC and external ADC.  I'm not convince
d I can't get a decent 12 bit ADC using an LVDS I/O.  The I/O banks have se
parate power and ground pins, so that reduces the switching currents.  Also
, this is a very low power chip.  It's not your city dimmer Virtex.  

The irony is I wanted to go with a Gowin part because of the limited I/O co
unt and lack of LVDS on the iCE40 Ultra parts.  Moving the ADC to a dedicat
ed chip frees up enough I/Os the iCE40 Ultra 39 I/O count works.  Still nee
d a comparator or two for other functions that could be in the FPGA.  I sup
pose I could justify the Gowin part in the 48QFN which still has LVDS for c
omparators.  

I just got a call from Edge, a Gowin distributor.  I guess they take seriou
sly inquiries of qty 10,000.  

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  Rick C.

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Re: ADCs in FPGAs
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
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a is a good way to go as it can be done all digitally, or almost so.  I'm n
ot completely clear on how to do it.  
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hey use an RC filter on the output bit as the reference voltage for the inp
ut.  I'm having trouble relating this to the typical block diagram of the s
igma delta converter.  Is this circuit the same thing?  
Quoted text here. Click to load it

I'd say it is a delta modulator not a delta-sigma modulator



Re: ADCs in FPGAs
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, snipped-for-privacy@gmail.com w
rote:
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lta is a good way to go as it can be done all digitally, or almost so.  I'm
 not completely clear on how to do it.  
Quoted text here. Click to load it
 They use an RC filter on the output bit as the reference voltage for the i
nput.  I'm having trouble relating this to the typical block diagram of the
 sigma delta converter.  Is this circuit the same thing?  
Quoted text here. Click to load it

Sorry, I'm not clear on what distinction you are trying to make.  First, wh
at is "it"?  

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  Rick C.

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Re: ADCs in FPGAs
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
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 wrote:
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delta is a good way to go as it can be done all digitally, or almost so.  I
'm not completely clear on how to do it.  
Quoted text here. Click to load it
.  They use an RC filter on the output bit as the reference voltage for the
 input.  I'm having trouble relating this to the typical block diagram of t
he sigma delta converter.  Is this circuit the same thing?  
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what is "it"?  
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the commonly used "RC filter on the output bit used as reference voltage" I
'd call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage
 fixed








Re: ADCs in FPGAs
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, snipped-for-privacy@gmail.c
om wrote:
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om wrote:
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a delta is a good way to go as it can be done all digitally, or almost so.  
 I'm not completely clear on how to do it.  
Quoted text here. Click to load it
or.  They use an RC filter on the output bit as the reference voltage for t
he input.  I'm having trouble relating this to the typical block diagram of
 the sigma delta converter.  Is this circuit the same thing?  
Quoted text here. Click to load it
, what is "it"?  
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 I'd call a delta modulator
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ge fixed

Ok, I understand what you mean now.  That is what I was asking about.  Than
ks

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Re: ADCs in FPGAs
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, snipped-for-privacy@gmail.c
om wrote:
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om wrote:
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a delta is a good way to go as it can be done all digitally, or almost so.  
 I'm not completely clear on how to do it.  
Quoted text here. Click to load it
or.  They use an RC filter on the output bit as the reference voltage for t
he input.  I'm having trouble relating this to the typical block diagram of
 the sigma delta converter.  Is this circuit the same thing?  
Quoted text here. Click to load it
, what is "it"?  
Quoted text here. Click to load it
 I'd call a delta modulator
Quoted text here. Click to load it
ge fixed

Here is my thinking.  Some people talk about digital noise being the source
 of noise limitations in this technique.  The I/O bank on FPGAs are separat
e from the rest of the chip and each other.  We have plenty of spare I/Os s
o we can dedicate a bank to ADC use.  Then the I/Os for the ADC are not jus
t less noisy, but also it can be provided by it's own supply with lower noi
se and better accuracy... or more like tracking the 5 volt rail that powers
 the sensors.  

I've been mulling the distinction between delta-sigma (or sigma-delta, I ca
n never remember) and the delta modulator.  A simple mod to the analog circ
uit should make it a delta-sigma.  

Vref -----------------| Vin-
                      |
Vin ---RRR---o---o----| Vin+
             |   |    |
             R  ---   |
             R  ---   |
             R   |    |
             |   V    |
             |        |
             +--------| SD out

This should provide the integration and quantization to be sigma-delta, rig
ht?  

The part I'm not clear on is turning the bit stream into a number.  I belie
ve the Lattice design simply counts the 1's on the comparator output.  Does
 that constitute a first order filter?  

We can run this input at up to 33 MHz.  At that rate we should have plenty  
of samples to work with.  Do you think we could potentially eke out a solid
 12 bits of performance with a sample rate of 1 kHz?  

I've seen this discussed a lot, but never ran into anyone who has done it.  
 We now have four or five people on the electronic design part and things a
re moving so fast, I'm not sure there will be time to give this proper cons
ideration.  Even though the motor, mechanicals and other parts are not desi
gned fully yet they want to push on the circuit board.  

Someone said they had used an instantiated ADC in the Xilinx tools.  Anyone
 know if that is actually an ADC or if it is an ADC chip interface?  

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Re: ADCs in FPGAs
On 2020-10-23 Rick C wrote in comp.arch.fpga:
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On what Xilinx device? At least the Zynq devices do have actual ADC's.

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Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

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Re: ADCs in FPGAs
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
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yone know if that is actually an ADC or if it is an ADC chip interface?  
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Don't know yet.  I'm asking questions, but he specifically said instantiate
d "IP" but I suppose that might be the same as "instantiating" a clock bloc
k with PLL ect.  

I'm essentially interviewing him to work on this open source project and th
e real issue is how much he knows about delta-sigma converters and how to i
mplement them.  

Right now I'd like to get an idea of whether it would significantly improve
 accuracy and/or noise to use separate comparator and driver for the analog
 interface.  The sensors are powered from 5 volts and so produce a 5 volt a
nalog output.  The separate drivers and comparators could be powered from t
he same supply, separate from any other supply on the board for noise isola
tion.  Also, as the sensor outputs are proportional to the power rail volta
ge, this will make all measurements ratiometric eliminating the need to cor
rect for the power voltages.  Otherwise we need to provide the I/O bank 3.3
 volts that is a ratioed to the 5 volt rail. I guess no big deal.  The poin
t is it's not that much more to use separate comparators and drivers and ma
y get us noise and accuracy advantages.  

Sorry if this sounds irrelevant.  I often uses newsgroup posts to solidify  
my thinking.  In this case we have tons of I/Os available, so I think I'm g
oing to use both approaches and dedicate a bank of I/Os to the ADCs.  

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Re: ADCs in FPGAs
fredag den 23. oktober 2020 kl. 20.07.58 UTC+2 skrev Rick C:
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Anyone know if that is actually an ADC or if it is an ADC chip interface?  
  
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ted "IP" but I suppose that might be the same as "instantiating" a clock bl
ock with PLL ect.  
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the real issue is how much he knows about delta-sigma converters and how to
 implement them.  
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ve accuracy and/or noise to use separate comparator and driver for the anal
og interface.  The sensors are powered from 5 volts and so produce a 5 volt
 analog output.  The separate drivers and comparators could be powered from
 the same supply, separate from any other supply on the board for noise iso
lation.  Also, as the sensor outputs are proportional to the power rail vol
tage, this will make all measurements ratiometric eliminating the need to c
orrect for the power voltages.  Otherwise we need to provide the I/O bank 3
.3 volts that is a ratioed to the 5 volt rail. I guess no big deal.  The po
int is it's not that much more to use separate comparators and drivers and  
may get us noise and accuracy advantages.  
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y my thinking.  In this case we have tons of I/Os available, so I think I'm
 going to use both approaches and dedicate a bank of I/Os to the ADCs.  
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if you need to add external parts you might as well add a real adc



Re: ADCs in FPGAs
On Friday, October 23, 2020 at 5:00:38 PM UTC-4, snipped-for-privacy@gmail.com  
wrote:
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  Anyone know if that is actually an ADC or if it is an ADC chip interface?
  
Quoted text here. Click to load it
.
iated "IP" but I suppose that might be the same as "instantiating" a clock  
block with PLL ect.  
Quoted text here. Click to load it
d the real issue is how much he knows about delta-sigma converters and how  
to implement them.  
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rove accuracy and/or noise to use separate comparator and driver for the an
alog interface.  The sensors are powered from 5 volts and so produce a 5 vo
lt analog output.  The separate drivers and comparators could be powered fr
om the same supply, separate from any other supply on the board for noise i
solation.  Also, as the sensor outputs are proportional to the power rail v
oltage, this will make all measurements ratiometric eliminating the need to
 correct for the power voltages.  Otherwise we need to provide the I/O bank
 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal.  The  
point is it's not that much more to use separate comparators and drivers an
d may get us noise and accuracy advantages.  
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ify my thinking.  In this case we have tons of I/Os available, so I think I
'm going to use both approaches and dedicate a bank of I/Os to the ADCs.  
  
Quoted text here. Click to load it

Not all parts are the same.  The ADCs that give more than 12 bits on multip
le channels are in the $5 and up range.  I can get comparators for a quarte
r and CMOS buffers for a dime.  I'm not sure the comparators are needed.  T
he buffer might help though.  

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Re: ADCs in FPGAs
On 24/10/2020 05:30, Rick C wrote:
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You are  a bit out on price, you can buy an 8 channel part from  
Microchip at about $3 5k off, MCP3464 (16 bit, 8 single ended or 4  
differential channels).
That way you get a fully sorted part with with built in PGA and you  
won't be at the mercy of using unspecified performance of the FPGA.

It would save you endless heartache in approval and  
certification/qualification time - I certainly wouldn't want to get  
involved with the FMEA for the FPGA sigma-delta design.

There may well be cheaper parts than this.

MK

Re: ADCs in FPGAs
On 24/10/2020 10:24, Michael Kellett wrote:
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It is also going to be dependent on the tolerances of the other parts -
the resistors, capacitors, buffers.

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There are also lots of microcontrollers with quite reasonable
multi-channel ADC's and lower prices than this.  They are usually not so
good for high resolution, but you can do other things with the
microcontroller too.

And for higher resolution requirements, the effort to make your own and
be sure it is accurate would seem ridiculous.  How many hundreds of
thousands of systems are you making where the development costs of
rolling your own ADC, testing and qualifying it save the cost of buying one?


Re: ADCs in FPGAs
On Saturday, October 24, 2020 at 4:24:31 AM UTC-4, Michael Kellett wrote:
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com wrote:
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  Anyone know if that is actually an ADC or if it is an ADC chip interface?
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s.
ntiated "IP" but I suppose that might be the same as "instantiating" a cloc
k block with PLL ect.
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and the real issue is how much he knows about delta-sigma converters and ho
w to implement them.
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mprove accuracy and/or noise to use separate comparator and driver for the  
analog interface.  The sensors are powered from 5 volts and so produce a 5  
volt analog output.  The separate drivers and comparators could be powered  
from the same supply, separate from any other supply on the board for noise
 isolation.  Also, as the sensor outputs are proportional to the power rail
 voltage, this will make all measurements ratiometric eliminating the need  
to correct for the power voltages.  Otherwise we need to provide the I/O ba
nk 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal.  Th
e point is it's not that much more to use separate comparators and drivers  
and may get us noise and accuracy advantages.
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idify my thinking.  In this case we have tons of I/Os available, so I think
 I'm going to use both approaches and dedicate a bank of I/Os to the ADCs.
Quoted text here. Click to load it
ltiple channels are in the $5 and up range.  I can get comparators for a qu
arter and CMOS buffers for a dime.  I'm not sure the comparators are needed
.  The buffer might help though.
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Which aspects of the FPGA impact the performance of a delta-sigma ADC?  Or  
even a single slope ADC?  The only relevant aspect would be the voltage dro
p from Vcc/ground to the output drive which is going to be very small when  
driving low currents.  

As I said, there will be an ADC on board for testing.  Then we will choose  
the method that works best for our goals.  

No risk, no worries.  

If anything, having the delta-sigma ADC as a backup to the chip ADC reduces
 the risk if there is a glitch with the chip.  It's not like ICs never have
 problems.  

$0.10 is still a lot better than $3.50.  

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Re: ADCs in FPGAs
I've been messing with this for a bit and the ultimate limitation seems to  
me to not be the digital noise in the FPGA, but rather the imbalance in the
 edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os a
re the part that matter to the analog portion of the ADC and they have sepa
rate Vcco from the core and also one another. I've been planning to dedicat
e a bank to the ADCs. But the input signals have a 5 volt range and will re
quire a 3.3 Vcco that is ratiometric to the 5 volt supply. It seems simpler
 to add a 5 volt level shifter and let that be powered by the sensor 5 volt
 rail.

So now I'm looking for the right buffer device and I'm starting to realize  
the limitation is the symmetry in the rise/fall times and the propagation d
elays of the two edges. Buffers are not so good with this having delays of  
single digit ns, but also lack of symmetry of single digit ns. With 30 ns p
ulses, that would add up. I thought analog switches might be better, but th
ey are worse with unbalanced switching times being hard to get into the low
 single digit ns. Many of the parts I find are LVC which require 3.3 volt p
ower to get compatible input levels.  I guess that's what the L is for in L
VC, duh!  

Anyone know of parts that would be good for this? Would it make sense to ru
n through two buffers at least conceptually balancing the rise/fall times a
nd prop delays? But then the delays start to add up, but that probably does
n't matter as much.

I found the 74ACT244 which seems to be the best fit so far.  5V power, TTL  
inputs to be compatible with 3.3V CMOS, balanced HL and LH propagation time
s and balanced H and L drive capabilities.  The prop delay can be up to 9 n
s which is a significant portion of the 30 ns cycle time, but that should n
ot be a significant factor.  

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Re: ADCs in FPGAs
On 23/10/2020 19:07:53, Rick C wrote:
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Nothing wrong with thinking out loud.

Like another poster has suggested, and unless there is a tight budget in  
terms of space or money, it can be cost effective in terms of design  
time (and cost) to simply fit a known ADC to the PCB that has a known  
spec and reduce overall risk.

--  
Mike Perkins
Video Solutions Ltd
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Re: ADCs in FPGAs
On Friday, October 23, 2020 at 9:00:37 PM UTC-4, Mike Perkins wrote:
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There will be a socket on the board for an ADC chip.  I'm not going to risk
 a board spin just for this idea.  Risk mitigation.  But at $5 each signifi
cant money can be saved in production by using an integrated ADC in the FPG
A.  

We actually don't need more than 10 bits for anything other than one sensor
 that will spend most of it's time in the very low end of the range.  If I  
can get 12 useful bits we are probably ok.  Using a single slope converter  
with calibration by measuring a Vref I can probably get better resolution a
t the low end and still have good results with the simpler circuit.  

I'm not sure how much "noise" will be a problem.  The absolute accuracy is  
limited by the sensors to a couple percent.  But we need good resolution fo
r the control loop and for the flow rate which we are integrating into a vo
lume.  

Sometimes I talk myself into this being a snap and other times I worry it w
on't work worth a damn.  

The delta-sigma circuits can be designed so they can be built to work with  
a mid-scale Vref and then allow for a single slope configuration with a com
mon slope circuit.  I was planning on using something like the single slope
 converter with the slower signals anyway.  I should probably design someth
ing so it can be tested without involving the sensors since it will be hard
 to manipulate them to get a particular output voltage.  

Or I can convince the group we should use digital sensors.  Lol!  Not sure  
why we picked analog sensors.  I'm having trouble finding anyone who carrie
s stock on a board mounted differential pressure sensor other than the one  
we are using.  The gage pressure sensor is available with a digital output  
though.  Only $10.  

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Re: ADCs in FPGAs
On 24/10/2020 07:08:17, Rick C wrote:
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Sounds like best of both worlds.

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That's still only a few mV of noise threshold.

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I might use a standard comparator rather than rely on an input with a  
noisy threshold. Not mentioning the violation of rise times.

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My experience of off-board third party digital sensors isn't a happy one  
with I2C sensors locking up on a glitch and having to reset them on the fly.

YMMV



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Mike Perkins
Video Solutions Ltd
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