ADCs in FPGAs

I would not be confident at getting 12 bits accuracy inside a fast digital part - it's very difficult to have your supplies and references stable enough, and to avoid switching noise from the digital parts interfering with the analogue. A 1 kHz sample rate 14-bit ADC chip with

I've never tried - getting a decent ADC into a functioning FPGA seems like a very difficult task. Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4 will do you, it has programmable gain, multiplexer, choice of up to 8 channels, 15 ENOB etc.

MK

lta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it.

They use an RC filter on the output bit as the reference voltage for the i nput. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

tion with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a s olid 12 bits of accuracy... the word width can be wider if that helps any.

Yes, I looked at that part. It's not as available as our target which is 1

0,000 stocked... yes, that may sound unrealistic, but many devices meet tha t requirement even if the FPGAs typically don't. Also it is a bit complica ted to use. Configuring it from an FPGA is a bother... configuring it from anything is a bother. lol But it certainly is an option. Very likely I will include both options, internal ADC and external ADC. I'm not convince d I can't get a decent 12 bit ADC using an LVDS I/O. The I/O banks have se parate power and ground pins, so that reduces the switching currents. Also , this is a very low power chip. It's not your city dimmer Virtex.

The irony is I wanted to go with a Gowin part because of the limited I/O co unt and lack of LVDS on the iCE40 Ultra parts. Moving the ADC to a dedicat ed chip frees up enough I/Os the iCE40 Ultra 39 I/O count works. Still nee d a comparator or two for other functions that could be in the FPGA. I sup pose I could justify the Gowin part in the 48QFN which still has LVDS for c omparators.

I just got a call from Edge, a Gowin distributor. I guess they take seriou sly inquiries of qty 10,000.

--

  Rick C. 

  + Get 1,000 miles of free Supercharging 
  + Tesla referral code - https://ts.la/richard11209

mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:

a is a good way to go as it can be done all digitally, or almost so. I'm n ot completely clear on how to do it.

hey use an RC filter on the output bit as the reference voltage for the inp ut. I'm having trouble relating this to the typical block diagram of the s igma delta converter. Is this circuit the same thing?

I'd say it is a delta modulator not a delta-sigma modulator

On Monday, August 31, 2020 at 5:43:54 PM UTC-4, snipped-for-privacy@gmail.com w rote:

lta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it.

They use an RC filter on the output bit as the reference voltage for the i nput. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

Sorry, I'm not clear on what distinction you are trying to make. First, wh at is "it"?

--

  Rick C. 

  -- Get 1,000 miles of free Supercharging 
  -- Tesla referral code - https://ts.la/richard11209

tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:

delta is a good way to go as it can be done all digitally, or almost so. I 'm not completely clear on how to do it.

. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of t he sigma delta converter. Is this circuit the same thing?

what is "it"?

the commonly used "RC filter on the output bit used as reference voltage" I 'd call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

a delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it.

or. They use an RC filter on the output bit as the reference voltage for t he input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

, what is "it"?

I'd call a delta modulator

ge fixed

Ok, I understand what you mean now. That is what I was asking about. Than ks

--

  Rick C. 

  -+ Get 1,000 miles of free Supercharging 
  -+ Tesla referral code - https://ts.la/richard11209

a delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it.

or. They use an RC filter on the output bit as the reference voltage for t he input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

, what is "it"?

I'd call a delta modulator

ge fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separat e from the rest of the chip and each other. We have plenty of spare I/Os s o we can dedicate a bank to ADC use. Then the I/Os for the ADC are not jus t less noisy, but also it can be provided by it's own supply with lower noi se and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I've been mulling the distinction between delta-sigma (or sigma-delta, I ca n never remember) and the delta modulator. A simple mod to the analog circ uit should make it a delta-sigma.

Vref -----------------| Vin- | Vin ---RRR---o---o----| Vin+ | | | R --- | R --- | R | | | V | | | +--------| SD out

This should provide the integration and quantization to be sigma-delta, rig ht?

The part I'm not clear on is turning the bit stream into a number. I belie ve the Lattice design simply counts the 1's on the comparator output. Does that constitute a first order filter?

We can run this input at up to 33 MHz. At that rate we should have plenty of samples to work with. Do you think we could potentially eke out a solid 12 bits of performance with a sample rate of 1 kHz?

I've seen this discussed a lot, but never ran into anyone who has done it. We now have four or five people on the electronic design part and things a re moving so fast, I'm not sure there will be time to give this proper cons ideration. Even though the motor, mechanicals and other parts are not desi gned fully yet they want to push on the circuit board.

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

--

  Rick C. 

  +- Get 1,000 miles of free Supercharging 
  +- Tesla referral code - https://ts.la/richard11209

On 2020-10-23 Rick C wrote in comp.arch.fpga:

On what Xilinx device? At least the Zynq devices do have actual ADC's.

--
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail) 

I'm a fuschia bowling ball somewhere in Brittany

fredag den 23. oktober 2020 kl. 07.10.53 UTC+2 skrev Rick C:

gma delta is a good way to go as it can be done all digitally, or almost so . I'm not completely clear on how to do it.

ator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

st, what is "it"?

e" I'd call a delta modulator

tage fixed

ce of noise limitations in this technique. The I/O bank on FPGAs are separ ate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not j ust less noisy, but also it can be provided by it's own supply with lower n oise and better accuracy... or more like tracking the 5 volt rail that powe rs the sensors.

can never remember) and the delta modulator. A simple mod to the analog ci rcuit should make it a delta-sigma.

ight?

yes with the voltage on Vin almost constant it should be an ok approximatio n, how well it works in practice I don't know

ieve the Lattice design simply counts the 1's on the comparator output. Do es that constitute a first order filter?

number of 1's ever a period should aka. integrate and dump has a sinc frequ ency response

y of samples to work with. Do you think we could potentially eke out a sol id 12 bits of performance with a sample rate of 1 kHz?

I don't know, I think only of the Xilinx app notes has some examples of per formance

. We now have four or five people on the electronic design part and things are moving so fast, I'm not sure there will be time to give this proper co nsideration. Even though the motor, mechanicals and other parts are not de signed fully yet they want to push on the circuit board.

ne know if that is actually an ADC or if it is an ADC chip interface?

some Xilinx ICs has buildin ADC, with a as far as I know optimistic 12bit

yone know if that is actually an ADC or if it is an ADC chip interface?

Don't know yet. I'm asking questions, but he specifically said instantiate d "IP" but I suppose that might be the same as "instantiating" a clock bloc k with PLL ect.

I'm essentially interviewing him to work on this open source project and th e real issue is how much he knows about delta-sigma converters and how to i mplement them.

Right now I'd like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt a nalog output. The separate drivers and comparators could be powered from t he same supply, separate from any other supply on the board for noise isola tion. Also, as the sensor outputs are proportional to the power rail volta ge, this will make all measurements ratiometric eliminating the need to cor rect for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The poin t is it's not that much more to use separate comparators and drivers and ma y get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I'm g oing to use both approaches and dedicate a bank of I/Os to the ADCs.

--

  Rick C. 

  ++ Get 1,000 miles of free Supercharging 
  ++ Tesla referral code - https://ts.la/richard11209

sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it.

arator. They use an RC filter on the output bit as the reference voltage f or the input. I'm having trouble relating this to the typical block diagra m of the sigma delta converter. Is this circuit the same thing?

irst, what is "it"?

age" I'd call a delta modulator

oltage fixed

urce of noise limitations in this technique. The I/O bank on FPGAs are sep arate from the rest of the chip and each other. We have plenty of spare I/ Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it's own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that po wers the sensors.

I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

right?

ion,

Not sure what you mean about constant Vin. Vin is the signal being measure d. Of course it needs to be band limited, but a main point of delta-sigma is that band is at the Nyquist rate of the input samples, a much wider band than the output band.

I'm also not sure why you refer to this as an approximation. The resistors are performing the difference of the input and the feedback. The cap is t he integrator. I suppose it's not a perfect integrator. Is it essentially equivalent to the other input circuit with the signal input as Vref and an RC from the feedback output to the differential input? Our decimation fac tor will be on the order of 32kibi.

One difference is the original circuit will run the inputs over a common mo de range of 0 to Vcc. The above circuit will keep the inputs near Vref.

elieve the Lattice design simply counts the 1's on the comparator output. Does that constitute a first order filter?

quency

Yeah, I know that. I just haven't done it before myself, so I'm unsure of what works well and what doesn't.

nty of samples to work with. Do you think we could potentially eke out a s olid 12 bits of performance with a sample rate of 1 kHz?

erformance

it. We now have four or five people on the electronic design part and thin gs are moving so fast, I'm not sure there will be time to give this proper consideration. Even though the motor, mechanicals and other parts are not designed fully yet they want to push on the circuit board.

yone know if that is actually an ADC or if it is an ADC chip interface?

Not using Xilinx for many reasons, but the big one is cost. Xilinx is grea t if you are designing dense FPGAs, but not so good if you are using an FPG A like one of the small ARM devices. Gowin has good packages and lots of d ifferential I/Os and great pricing. Lattice has some good packages, but se em to have dropped the ball on the I/Os, very limited differential options in the good packages. I wouldn't be using Gowin otherwise.

--

  Rick C. 

  --- Get 1,000 miles of free Supercharging 
  --- Tesla referral code - https://ts.la/richard11209

fredag den 23. oktober 2020 kl. 20.28.58 UTC+2 skrev Rick C:

y sigma delta is a good way to go as it can be done all digitally, or almos t so. I'm not completely clear on how to do it.

mparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diag ram of the sigma delta converter. Is this circuit the same thing?

First, what is "it"?

ltage" I'd call a delta modulator

voltage fixed

source of noise limitations in this technique. The I/O bank on FPGAs are s eparate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are n ot just less noisy, but also it can be provided by it's own supply with low er noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

, I can never remember) and the delta modulator. A simple mod to the analo g circuit should make it a delta-sigma.

a, right?

ation,

red.

I meant Vin+ the comparator input

that band is at the Nyquist rate of the input samples, a much wider band th an the output band.

rs are performing the difference of the input and the feedback. The cap is the integrator. I suppose it's not a perfect integrator. Is it essential ly equivalent to the other input circuit with the signal input as Vref and an RC from the feedback output to the differential input? Our decimation f actor will be on the order of 32kibi.

an ideal integrator would charge the cap with a current proportional to the Vin for that to happen Vin+ would need to be constant, it isn't quite

Anyone know if that is actually an ADC or if it is an ADC chip interface?

ted "IP" but I suppose that might be the same as "instantiating" a clock bl ock with PLL ect.

the real issue is how much he knows about delta-sigma converters and how to implement them.

ve accuracy and/or noise to use separate comparator and driver for the anal og interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise iso lation. Also, as the sensor outputs are proportional to the power rail vol tage, this will make all measurements ratiometric eliminating the need to c orrect for the power voltages. Otherwise we need to provide the I/O bank 3 .3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The po int is it's not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

y my thinking. In this case we have tons of I/Os available, so I think I'm going to use both approaches and dedicate a bank of I/Os to the ADCs.

if you need to add external parts you might as well add a real adc

Nothing wrong with thinking out loud.

Like another poster has suggested, and unless there is a tight budget in terms of space or money, it can be cost effective in terms of design time (and cost) to simply fit a known ADC to the PCB that has a known spec and reduce overall risk.

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

sly sigma delta is a good way to go as it can be done all digitally, or alm ost so. I'm not completely clear on how to do it.

comparator. They use an RC filter on the output bit as the reference volta ge for the input. I'm having trouble relating this to the typical block di agram of the sigma delta converter. Is this circuit the same thing?

. First, what is "it"?

voltage" I'd call a delta modulator

ce voltage fixed

e source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spar e I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it's own supply with l ower noise and better accuracy... or more like tracking the 5 volt rail tha t powers the sensors.

ta, I can never remember) and the delta modulator. A simple mod to the ana log circuit should make it a delta-sigma.

lta, right?

imation,

sured.

s that band is at the Nyquist rate of the input samples, a much wider band than the output band.

tors are performing the difference of the input and the feedback. The cap is the integrator. I suppose it's not a perfect integrator. Is it essenti ally equivalent to the other input circuit with the signal input as Vref an d an RC from the feedback output to the differential input? Our decimation factor will be on the order of 32kibi.

he Vin

But that is a minor issue, second order at least since the action of the fe edback will keep Vin+ very close to Vref. The Vin signal has no more weigh t than the feedback output so worst case if the input pegs at some point th e feedback output will also peg and Vcap remains the same.

I see Lattice actually shows both input arrangements in their design note o nly saying the one above uses an extra resistor and I guess the Vref. They do mention that using Vref sets the point of operation. I don't think the differential inputs on the FPGAs are intended to range up and down the vol tage scale so fixing it is useful. I suppose some scaling error can be rem oved by setting Vref with a 50/50 duty cycle output onto a similar RC. We will have several ADC, so Vref can be shared between them.

For a while I was thinking a single slope ADC could be used. Then Vref wou ld need to be either a linear ramp or if an RC is used a log compensation w ould be needed once digitized. This can give 15 bits of resolution at 1 kS PS, but by ramping from Vcc to ground more resolution can be obtained at th e low end which is useful for some of the inputs. Don't know about ENOB th ough. It would factor in Vcc so be a ratiometric measurement which is what we need. It's much simpler than the delta-sigma approach for sure. We ha ve to do calculations on the measurements including a zero offset so adding a scale factor to compensate for the RC inaccuracy is not a big deal (meas uring a Vref periodically). One of the measurements requires a divide to a ccount for absolute pressure, so once we have a divide it can be used for a ny of the calcs. I guess this would require good temperature compensation in the RC. Either in the circuitry or in the calculations. We'll have a t emperature measurement on the board.

--

  Rick C. 

  --+ Get 1,000 miles of free Supercharging 
  --+ Tesla referral code - https://ts.la/richard11209

Anyone know if that is actually an ADC or if it is an ADC chip interface?

.

iated "IP" but I suppose that might be the same as "instantiating" a clock block with PLL ect.

d the real issue is how much he knows about delta-sigma converters and how to implement them.

rove accuracy and/or noise to use separate comparator and driver for the an alog interface. The sensors are powered from 5 volts and so produce a 5 vo lt analog output. The separate drivers and comparators could be powered fr om the same supply, separate from any other supply on the board for noise i solation. Also, as the sensor outputs are proportional to the power rail v oltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it's not that much more to use separate comparators and drivers an d may get us noise and accuracy advantages.

ify my thinking. In this case we have tons of I/Os available, so I think I 'm going to use both approaches and dedicate a bank of I/Os to the ADCs.

Not all parts are the same. The ADCs that give more than 12 bits on multip le channels are in the $5 and up range. I can get comparators for a quarte r and CMOS buffers for a dime. I'm not sure the comparators are needed. T he buffer might help though.

--

  Rick C. 

  -+- Get 1,000 miles of free Supercharging 
  -+- Tesla referral code - https://ts.la/richard11209

There will be a socket on the board for an ADC chip. I'm not going to risk a board spin just for this idea. Risk mitigation. But at $5 each signifi cant money can be saved in production by using an integrated ADC in the FPG A.

We actually don't need more than 10 bits for anything other than one sensor that will spend most of it's time in the very low end of the range. If I can get 12 useful bits we are probably ok. Using a single slope converter with calibration by measuring a Vref I can probably get better resolution a t the low end and still have good results with the simpler circuit.

I'm not sure how much "noise" will be a problem. The absolute accuracy is limited by the sensors to a couple percent. But we need good resolution fo r the control loop and for the flow rate which we are integrating into a vo lume.

Sometimes I talk myself into this being a snap and other times I worry it w on't work worth a damn.

The delta-sigma circuits can be designed so they can be built to work with a mid-scale Vref and then allow for a single slope configuration with a com mon slope circuit. I was planning on using something like the single slope converter with the slower signals anyway. I should probably design someth ing so it can be tested without involving the sensors since it will be hard to manipulate them to get a particular output voltage.

Or I can convince the group we should use digital sensors. Lol! Not sure why we picked analog sensors. I'm having trouble finding anyone who carrie s stock on a board mounted differential pressure sensor other than the one we are using. The gage pressure sensor is available with a digital output though. Only $10.

--

  Rick C. 

  -++ Get 1,000 miles of free Supercharging 
  -++ Tesla referral code - https://ts.la/richard11209

You are a bit out on price, you can buy an 8 channel part from Microchip at about $3 5k off, MCP3464 (16 bit, 8 single ended or 4 differential channels). That way you get a fully sorted part with with built in PGA and you won't be at the mercy of using unspecified performance of the FPGA.

It would save you endless heartache in approval and certification/qualification time - I certainly wouldn't want to get involved with the FMEA for the FPGA sigma-delta design.

There may well be cheaper parts than this.

MK