Latest threads in Field-Programmable Gate Arrays

What is value of scale_sch for FFT5.0 IP core for IFFT

We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2 burst mode,natural order,scaling(so get same o/p s...

0 14yrs

VARUN_AGR

0 14yrs VARUN_AGR

VCD to power consumption trace

Hi all, I have captured the toggle counts of my design in a VCD file and I wonder if there are now any tools available...

2 14yrs

patrick.bateman26

2 14yrs patrick.bateman26

ABEL to VHDL/Verilog converter

Hi, where i can get the tool to ocnvert ABEL HDL to VHDL/verilog converter. Thanks & Regards, sheik --------------------...

2 14yrs

ksheik.abdul

2 14yrs ksheik.abdul

Effective square root algorithms implemented on FPGAs already

Hello guys, I'm trying to find a little bit more information for efficient square root algorithms which are most likely...

8 14yrs

dimitar_petrov

8 14yrs dimitar_petrov

Virtex 5 GC clock pin vs GC//CC clock pins

Hi, What is the difference between a GC clock pin and a GC/CC clock pin(I dont mean a CC pin I mean a GC/CC pin)? Such...

1 14yrs

michael_laajanen

1 14yrs michael_laajanen

balancing IIR filter (after adding extra registers)

I designed a low pass IIR filter in starix iv but I got speed problem. I need to run it on 245MHz but can only achieve...

23 14yrs

kazimayob2

23 14yrs kazimayob2

XLNX efuse anyone?

(repost from XLNX forum) Has anyone succesfully managed to program the eFuses? On the Virtex-6 in particular but any de...

1 14yrs

mr.thomas.c.jones

1 14yrs mr.thomas.c.jones

opendous-jtag support for independent USB drivers for JTAG/Impact/Chipscope?

Hi, Probably most Linux users working with Xilinx tools use the excellent drivers written by Michael Gernoth and availa...

0 14yrs

wzab01

0 14yrs wzab01

Xilinx SRAM clock-to-out and input constraint with forwarded clock

Hi, I have SRAM connected to a FPGA. The clock is forwarded to the SRAM by the FPGA (using ODDR trick). The input clock...

1 14yrs

SomeOne

1 14yrs SomeOne

voltage drop on STRATIX FPGA supply planes

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop acr...

12 14yrs

colin_toogood

12 14yrs colin_toogood

Handling overflow in a self-repeating frequency counter

Hi guys. I'm currently working on the HDL code for an open-source project which images 'strange and unusual' magnetic m...

10 14yrs

philpem

10 14yrs philpem

Beginner question on FIFO in "FPGA prototyping by VHDL examples"

I am very new to FPGA programming. I'm using "FPGA Prototyping by VHDL examples" to learn VHDL. I've gotten up to secti...

8 14yrs

bfmackin

8 14yrs bfmackin

Trying to select a development board, can somebody help me make an informed choice?

Hello, I am trying to decide what board to order for a project I want to do betwee= n April and June in school, and for...

5 14yrs

jurgen.defurne

5 14yrs jurgen.defurne

slimming down ISE install

Just installed ISE webpack 13.3 on my laptop and things are getting a bit tight space-wise - a lot of space (several gb...

3 14yrs

mike

3 14yrs mike

Verilog module in VHDL project - ISE 13

I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VH...

1 14yrs

mike

1 14yrs mike