Field-Programmable Gate Arrays

Regarding FFT & IFFT CORE IN XILINX

Sir I am trying to use FFT 5.0 core in xilinx as follows for 50 hz Sin WAVE(THROUGH ADC)for noise removal 1. 64 Transfo...

0 comments posted 14yrs

posted by VARUN_AGR

0 comments posted 14yrs posted by VARUN_AGR

DEBUG a FIFO output on Virtex5 using CHIPESCOPE

Hi All, I'm a relatively newbe of FPGA development. We are working on a design involving BFSK modulator / demodulator p...

1 comments posted 14yrs

posted by fabio.giovagnini

1 comments posted 14yrs posted by fabio.giovagnini

This comp.arch.fpga group is suck - I'm leaving now

Dun't know why, this group being moderated or something? But some of my posts didn't make it. I thinks others would exp...

2 comments posted 14yrs

posted by ccon67

2 comments posted 14yrs posted by ccon67

Xilinx platform cable crashes SL6.1 box

Has anyone else experienced systems crashes caused by the Xilinx platform cable, it's happening to me a couple of times...

0 comments posted 14yrs

posted by schvantzkoph

0 comments posted 14yrs posted by schvantzkoph

Xilinx virtex-5 pitfalls

Hello People. Thought I'd share with you, the latest harvest of pitfalls when using xilinx virtex-5 (FX) FPGAs. Pitfall...

2 comments posted 14yrs

posted by removethis_finnstadel

2 comments posted 14yrs posted by removethis_finnstadel

Equivalence between "XtremeDSP48 slice" and "slices of programmable logic"

Hi folks! In this page (http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/dsp48e_top/) I've found this:...

3 comments posted 14yrs

posted by mazouz.nezhate

3 comments posted 14yrs posted by mazouz.nezhate

High-bandwidth Digital Content (HDCP) keys with FPGA?

Does anyone know how I could safekeep HDCP keys legally by implementing the HDCP (and HDMI/DisplayPort) engine in FPGA?...

0 comments posted 14yrs

posted by mleikvol

0 comments posted 14yrs posted by mleikvol

Clock distribution for ADC and jitter

Hi everyone, I've got a question regarding clocks and jitter. Let's say I have 2 ADCs that need an input clock of 80 MH...

7 comments posted 14yrs

posted by benjamin.couillard

7 comments posted 14yrs posted by benjamin.couillard

On-chip, high-speed CAN tranceiver in NXP LPC11Cxx

Hello, Who knows if the transceiver is really on-chip or if it is two die solution in one housing? Heinz

1 comments posted 14yrs

posted by hj.oertel

1 comments posted 14yrs posted by hj.oertel

D-Type Flip flop with negated Q in Webise for a schematic capture

Sorry for the naive question, but how do I capture a schematic with a D and J-K FF that do have negated Q? I tried to d...

15 comments posted 14yrs

posted by giuseppe.marullonospam

15 comments posted 14yrs posted by giuseppe.marullonospam

Lattice buys SiBlue for $62 million

I think this will be one of the more significant semiconductor acquisitions of the year. http://www.fpgagurus.edn.com/b...

2 comments posted 14yrs

posted by gnuarm

2 comments posted 14yrs posted by gnuarm

Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!

HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My cust...

1 comments posted 14yrs

posted by cwthomas

1 comments posted 14yrs posted by cwthomas

DDR2 read interface

Hello, I have a question regarding DDR2 memory controller. In a read operation from DDR2 based on strobe, do one need t...

1 comments posted 14yrs

posted by sachins.chadha

1 comments posted 14yrs posted by sachins.chadha

store data file in DDR2-SDRAM

Hi How can I load a data file to the DDR2-SDRAM. I'm use virtex 5 Ml507. I try to download my file with the XMD but whe...

0 comments posted 14yrs

posted by ghorbel.agnes

0 comments posted 14yrs posted by ghorbel.agnes

Horsepower On Tap

I was waiting for Quartus to finish crunching my latest build, and poking around idly on NewEgg trying to see what it w...

7 comments posted 14yrs

posted by rgaddi

7 comments posted 14yrs posted by rgaddi