Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

bad syncronous description

Hi, why is nstate bad syncronous? It works when I remove rising_edge(clk_250k)... (I want to generate a signal which is...
5 comments posted 21yrs
posted by benjamin
5 comments posted 21yrs posted by benjamin

what is microblaze ?

Hi, Can any1 tell me what exactly is microblaze or in particulat what do we mean by the term "soft processor" ?? If i h...
3 comments posted 21yrs
posted by manmeetbhangu
3 comments posted 21yrs posted by manmeetbhangu

[Sparan-II] Internal Power-On Reset Block?

Hi all, we face a strange problem with our synchronized reset signal coming from the ISA-Bus. It seems that some part o...
2 comments posted 21yrs
posted by meng.engineering
2 comments posted 21yrs posted by meng.engineering

ml310: linux boot faillure

I'm trying to use a montavista kernel on a ml310 but when I run it, I always have the same error even if I follow the x...
1 comments posted 21yrs
posted by olivierbrouse
1 comments posted 21yrs posted by olivierbrouse

Executing program from external memory

Hi, I'm using the ML 401 development board configured with the "reference design" provided by Xilinx. I need to downloa...
1 comments posted 21yrs
posted by pbs
1 comments posted 21yrs posted by pbs

Space Invaders!

Hi guys, hope you can help! I'm trying to create Space Invaders using video ROMs. I'm creating a hardware schematic to...
2 comments posted 21yrs
posted by sean_yzfr1
2 comments posted 21yrs posted by sean_yzfr1

New FPGA Development Board

A new product from Digiliant... All i can say is oooo! * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit...
20 comments posted 21yrs
posted by Ziggy
20 comments posted 21yrs posted by Ziggy

slow peripherals and modelsim

Hi, I am using a KS0066UP LCD Controller, which requires some delays in the ms area. However my FPGA runs at 100 MHz. T...
8 comments posted 21yrs
posted by benjamin
8 comments posted 21yrs posted by benjamin

simple delays

Hi, i am a newbee to FPGA design and i wanted to know how to add simple delay in my Spartan 3 XC3S200 FPGA. I have a 16...
3 comments posted 21yrs
posted by amir.intisar
3 comments posted 21yrs posted by amir.intisar

Platform Cable USB & ISE 7.1 & Linux

Could anybody confirm that the "Platform Cable USB" works (or not) with ISE 7.1 under Linux (preferably FC3) ? Thanks,...
0 comments posted 21yrs
posted by russelmann
0 comments posted 21yrs posted by russelmann

Relative number of CLBs

Hi Group, I am looking for some rough estimate kind of numbers. The numbers don't really need to be precise, just guess...
5 comments posted 21yrs
posted by akiriwas
5 comments posted 21yrs posted by akiriwas

READ/WRITE files using TEXTIO using Quartus

Hi, I am write and read from a text file using vhdl. I am using quartus 4.0 to compile and simulate. when I compile the...
1 comments posted 21yrs
posted by johngalil
1 comments posted 21yrs posted by johngalil

motherboard w/o 3.3V PCI fingers

hi there, i have been working on a PCI 5V DAQ card. there is a surprising fact that i have observed regarding the mothe...
1 comments posted 21yrs
posted by shyran
1 comments posted 21yrs posted by shyran

WTB Xilinx Ver. 6.2 EDK

I will pay you a reasonable fee for a copy of the Xilinx ver. 6.2 EDK with manuals. Also, I am looking to purchase ChipS...
0 comments posted 21yrs
posted by tod.adamson
0 comments posted 21yrs posted by tod.adamson