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Relative number of CLBs

Hi Group,

I am looking for some rough estimate kind of numbers. The numbers don't really need to be precise, just guesses and estimates.

Okay, here's what I need. What would the relative number of CLBs needed be for the following types of synthesized circuits (assuming the FPGA they were implemented on did NOT have any special components that would lessen the number of CLBs needed)

  1. 32 bit integer adder
  2. 32 bit integer multiplier
  3. 32 bit integer divider
  4. Double precision floating point adder (I know this one is expensive)
  5. Double precision floating point multiplier
  6. Double precision floating point divider
  7. Double precision floating point square root

I know there are different algorithms for some of these operations, some are parallel some are serial, just whichever you know would help. Rough guesses are all I need. If you want, just take whichever would be the lease, use that as a baseline of 1.0 for the relative sizes. Thanks everyone.

-AKiriwas

Reply to
akiriwas
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Reply to
Alex Freed

I agree, and eventually I will be doing just that on my old Spartan II. However, right now im just looking for some quick estimates from anyone that's already done these implementations. If no one responds I guess I will have to spend a week or so implementing all those. But thanks for the reponse.

-AKiriwas

Reply to
akiriwas

1 single cycle

32 single cycle or pipelined

25 32 cycle sequential

40 single cycle or pipelined

200 single cycle or pipelined
200 multi cycle (64?) sequential
210 multi cycle (64?) sequential

I bet some of these are off by 50%

Philip

Philip Freidin Fliptronics

Reply to
Philip Freidin

Thanks! But, I was almost sure that I had read that a floating point adder was much more expensive (in terms of slices or CLBs) than a floating point multiplier since it needed to normalize one of the operands. Was I wrong about this?

Reply to
akiriwas

Hey, they were just guesses. I guessed that since you ruled out any support logic (like the carry that is built into ALL logic elements of ALL current products, regardless of vendor), that also ruled out things like the multipliers that most current products also include. So I guessed that the multiplier array more or less was as big as as the normailzing logic. If you add in my +/- 50% wishy-washy ness, I am probably in the right ballpark, or at least the right time zone.

These are all fairly easy to code up for current synthesys tools, providing you arent trying to do all the silly exception stuff in IEEE 754.

Philip

Reply to
Philip Freidin

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