Field-Programmable Gate Arrays

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RocketIO attribute for TLK301 or TLK2501

Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.
0 comments posted 21yrs
posted by corify
0 comments posted 21yrs posted by corify

XC4k parts obsolete ?

This is a Question to Xilinx experts. One of our customers for whom we did design (not so long ago !) an XC4044XL repor...
10 comments posted 21yrs
posted by "info_"
10 comments posted 21yrs posted by "info_"

ISE wishlist

This is for the Xilinx guys on the newsgroup (sorry if you've heard this before): Could you make Picoblaze a standard p...
2 comments posted 21yrs
posted by send_no_spam_to_jimgeorge
2 comments posted 21yrs posted by send_no_spam_to_jimgeorge

MAX II UFM data specification and programming

Is there an easy way to convert a plain ascii file of hex numbers etc. into a SOF format or similar in order to program...
8 comments posted 21yrs
posted by newsmailcomp6
8 comments posted 21yrs posted by newsmailcomp6

Rom Inference

Hi all, I am using Synplify Pro for synthesis. My target FPGA is APEX20KE. I have the following code for rom but the at...
5 comments posted 21yrs
posted by am.imak
5 comments posted 21yrs posted by am.imak

Memec JTAG cable IJC-3

Hello, does anyone know the actual pin connections on a Memec JTAG cable IJC-3? The problem is that the connector has 9...
0 comments posted 21yrs
posted by losansky
0 comments posted 21yrs posted by losansky

dynamic size of ports

Hi all! I have a problem that someone here might have the answer to. I have a divider that takes inputs of 13 and 12 bi...
8 comments posted 21yrs
posted by dan.nilsen
8 comments posted 21yrs posted by dan.nilsen

PCI plug n play and Graphics card implementation

Hello all, Can someone please answer the following questions? 1. I am using a VGA graphics core with 60Hz refresh rate...
6 comments posted 21yrs
posted by mansoor.naseer
6 comments posted 21yrs posted by mansoor.naseer

Bus Frequency !!

Hi All I have read that the PLB bus can have a 1:1 ratio to the processor bus frequency. And when I was giving my initi...
0 comments posted 21yrs
posted by johnsons
0 comments posted 21yrs posted by johnsons

quartus_pgm under Linux?

According to byteblaster/INSTALL (in linux/byteblaster.tar.gz): " If you are using Quartus II 4.0 or later then you do...
5 comments posted 21yrs
posted by newsmailcomp6
5 comments posted 21yrs posted by newsmailcomp6

Sync + FIFO

Hi, what does have more advantages when trying to synchronize an incoming external datastream: 1. Synchronize the data...
40 comments posted 21yrs
posted by ALuPin
40 comments posted 21yrs posted by ALuPin

webpack for os x or freebsd ?

Has any one tried running 7.1 for linux on OS X or darwin or freebsd ? Even just commandline tools ? Trying to avoid hav...
2 comments posted 21yrs
posted by news
2 comments posted 21yrs posted by news

questions on Xilinx Virtex-4 to DDR SDRAM module

I have a few questions in the design of a connection from Xilinx Virtex-4 to DDR SDRAM 200-pin SO-DIMM module First is...
0 comments posted 21yrs
posted by wwqiao
0 comments posted 21yrs posted by wwqiao

Help creating a System Ace file

I have a 402 Virtex 4 board from Xilinx. I don't have one of the special cables required to load it so I am trying to u...
2 comments posted 21yrs
posted by Marco
2 comments posted 21yrs posted by Marco

Experience with Hitech Global & Xilinx

Has anyone experince with Hitech Global (www.hitechglobal.com) prototyping boards? Do they stick to their board manufac...
6 comments posted 21yrs
posted by simo.heinle
6 comments posted 21yrs posted by simo.heinle