Hi all!
I have a problem that someone here might have the answer to. I have a divider that takes inputs of 13 and 12 bits, and produces an output of
12 bits. I have a component to strip away the redundant bits from the divider, if the result of the division is, say an int value of 6, I don't want to use all 12 bits. This circuit is a part of an MPEG-4 device, a quantizer, so I want to compress as much as possible. My question is then, how do I declare the ports on the component that strips away the bits to output an std_logic_vector that is not fixed in size, but dynamic? This must be synthesizable. Guess there are many ways of doing this, and I hope someone has got an answer to me.Thanks,
Dan Nilsen