Latest threads in Field-Programmable Gate Arrays

fast universal compression scheme and its implementation in VHDL

Hi folks, my name is Jens and I am student of the Technical University Berlin. Through my course of study in microelect...

1 21yrs

quinn_the_esquimo

1 21yrs quinn_the_esquimo

SPD interface(Serial presence detect)

Hi all, I am implementing a SPD interface in an FPGA. The DDR SDRAM is from MICRON. Now to redd the EEPROM content(firs...

9 21yrs

praveen.kantharajapura

9 21yrs praveen.kantharajapura

I2C clock stretching(XILINX reference design)

Hi all, I am implementing a I2C slave. I am refering XAPP333 for my deisgn. But one of the "limitation" of that referen...

4 21yrs

praveen.kantharajapura

4 21yrs praveen.kantharajapura

Question for Alex Gibson

Hi Alex, I couldn't find your original email so I thought posting o CAStal Here's my original message > > Hi Alex > > I...

3 21yrs

dima_turbiner

3 21yrs dima_turbiner

JTAG programming: JAM files versus ISC (IEEE1532) files

Hi all, We want to implement a JTAG programmer in an Altera Stratix device to program a chain of EPC16 devices. The Str...

4 21yrs

mandana

4 21yrs mandana

Persist option in bitgen

Anybody have experience with the -g Persis:Yes option in bitgen? I tried using this option to be able to read back the...

0 21yrs

Hua.Zheng

0 21yrs Hua.Zheng

ISE tools to use SMP?

Does anybody know if ISE tools (bitgen, par, map, etc.) could utilize dual-core CPU's to speed up their process? I am u...

1 21yrs

Hua.Zheng

1 21yrs Hua.Zheng

Synplify/Quartus used to support direct to Hardcopy?

I seem to remember Synplicity and Quartus allowing the user to select an Altera Stratix Hardcopy device as the target d...

1 21yrs

statepenn99

1 21yrs statepenn99

pcb layers on BGAs Spartan-3

Hi all, I am new in this forum, and I have not found a question as th stated below. Sorry if it has already done. I hav...

27 21yrs

calaf_calaf_calaf

27 21yrs calaf_calaf_calaf

execute ppc code from external ram

We have made a memory controller which handles accesses from/to ddr sdram. A bootloader is running in bram and we downl...

1 21yrs

someone

1 21yrs someone

Mapping Dual Port Ram into Microblaze address space

Hallo, I have created a user logic template for obp bus with Create/Import Wizard of EDK with the feature: user logic a...

3 21yrs

marcotoschi_no_spam

3 21yrs marcotoschi_no_spam

How to convert Matlab to HDL?

Hi all, Is there any tools to convert Matlab M-language to HDL? Thanks! Best regards, Davy

3 21yrs

zhushenli

3 21yrs zhushenli

Ml40x Reference Design not working with EDK 7.1?

Hi all, I have been having problems with the EKD 7.1 and the ML40x reference design for quite some time now. ISE/EDK 7....

1 21yrs

pbs

1 21yrs pbs

Lattice LFEC20 DDR SDRAM connection

Tried weeks ago contacting Lattice without any response so far... Besides the DQS/data bit groups per bank...are all ot...

1 21yrs

me

1 21yrs me

Motion controller design with CPLD

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have de...

5 21yrs

engtech1

5 21yrs engtech1

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