SPD interface(Serial presence detect)

I2C EEPROMs come in more than one flavor. The simplest with up to 256 bytes use a single byte address. Larger ones need more address bytes. To access the data starting at zero, you must write zero to the EEPROM address register, if not you can get data starting at some random address.

For the small EEPROMs (which are big enough to store SPD for most applications) you would write zero (one byte) then read any number of bytes. The address increments after each read, whether or not you send them within one start-stop sequence. This is why you need to reset the address before you start reading.

You don't need to use a repeated start sequence to read the EEPROM. You can just do a simple write (one byte of address for small EEPROMs two or more for larger ones) followed by simple reads. Beware that writing too many bytes to the EEPROM can cause data to be written if the device is not write protected. i.e. if you have a 24C02 and send two bytes of zero, you'll clear the first byte in the EEPROM. Also if you write too many bytes you'll start reading after the byte written (byte 1 in the example just mentioned).

So to sum it briefly. Writing multiple bytes starts with the address register and continues with data. If the address register is one byte, only the first byte after the I2C address cycle goes to the address register and subsequent bytes go into the EEPROM starting at the address just written and incrementing with each byte. After the writes are done, the address register keeps its value which will point to the location after the last one written (or to the address written if no bytes were written to the EEPROM). Reading always starts from the location in the address register, which increments after each byte. You must write to force the address register to a known value before you start to read.

Regards, Gabor

Hi Gabor ,

Thanks for the reply. My EEPROM is write protected i will only be reading the first 128 bytes, is this flow diagram all right.

1-bit 8-bits 1-bit

Start from master --->> EEPROM Slave address("10100001") -->> ACK from eeprom --->>

8-bits 1-bit 8-bits 1-bit

Write register address "00000000" --->> ACk from EEPROM --->> Data[0] from EEPROM --->> ACK from master

8-bits 1-bit

................. --->>Data[127] from EEPROM --->> STOP from master

I will generate the STOP condition after receiving 128 bytes.

Any comments on this.

Regards, Praveen

Gabor wrote:

Actually you need to start with write address "10100000" in order to write the address register (you don't need to write the EEPROM array so write protect doesn't matter).

Right here you need to switch to read mode. There are two ways to do this. Either master sends Stop followed by Start or master sends repeated start. If you intend to reuse this code for other peripherals besides EEPROM, you'll find the repeated start is compatible with more chips.

Then you need to provide slave address "10100001" for read and get ack from slave then:

Also you talk about "bits" when you send start and stop. These conditions do not toggle the SCL line so they are not usually counted as "bits" as would be data or Ack cycles.

Regards, Gabor

Another point, if you haven't read the I2C specification yet it is available at:

It contains some good figures to illustrate the bus protocol.

Also this ap note:

has a useful table of assigned addresses and some more timing diagrams.

Links to more literature appear on this page:

Gabor wrote:

One additional note. As mentioned below, the master should ACK each byte that it reads, except for the last byte. The last byte should be nacked prior to the stop condition.

dbrown

How will the master know that this byte is the last byte, and what happens if the master acknowledges the last byte also.

Can you be more specific on what you mean by this? (are you referring to the SPD controller, or the state machine or microprocessor controlling it?)

Referring to the I2C spec Page 10, section 7.2, "If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition"

I don't really know what will happen with the slave device you are using if you don't NACK the last byte, it might work just fine, or if the SPD puts out one additional clock at the end of the ACK bit position to release the ACK/NACK, the slave device would think the next byte should be read and would assert the MSB of the next byte on the data line. If the MSB of the next byte was a 0, then the master would not be able to apply a stop condition (remember it's open drain or wire AND), and the system would affectively be unsynchronized. The Master may believe it terminated the the read sequence correctly, and the slave could still be driving the data line low with it's MSB waiting to shift out the next bit for the byte. Following communications to the slave device would fail, until the master outputs a continuous 1 (0xFF) pattern to the device allowing the device to eventually get a NACK and terminate the read operation. The master could then attempt to repeat the sequence for a read operation..

Based on the spec. and the possibilities of what you can look forward to and the corrective actions, I would recommend following it for compatibility reasons.

dbrown

I am referring to SPD controller.

Hi gabor, Thanks for the clarifications. The reading will basically happen in two phases.The flow is given below, i will start implementing the same. check it and reply if any clarifications.

**********READ PHASE 1**********

Step 1 I2C Start (master) S

Step 2 I2C General address (master) 1 0 1 0 0 0 0 0

Step 3 I2C Acknowledge (slave) A

Step 4 I2C write register address (master) 0 0 0 0 0 0 0 0

Step 5 I2C Acknowledge (slave) A

Step 6 I2C Stop (master) P

**********READ PHASE 2********** Step 7 I2C Start (master) S

Step 8 I2C General address (master) 1 0 1 0 0 0 0 1

Step 9 I2C Acknowledge (slave) A

Step 10 I2C Read data (slave) Data Data Data Data Data Data Data Data

Step 11=86 I2C Not acknowledge (master) A

Step 12 I2C Stop (master) P

=86Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.

Gabor wrote: